PC87360 Datasheet, PDF (147/168 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Protection and Extensive GPIO Support

9.0 Legacy Functional Blocks (Continued)
9.4.3
.
SP1 and SP2 Register Maps for UART Functionality
Table 48. Bank 0 Register Map
Offset Mnemonic
Register Name
Type
00h
RXD Receiver Data Port
RO
00h
TXD Transmitter Data Port
W
01h
IER Interrupt Enable
R/W
EIR Event Identification (Read Cycles)
RO
02h
FCR FIFO Control (Write Cycles)
W
LCR^{Note 1. Line Control}
03h
BSR^{Note 1. Bank Select}
R/W
04h
MCR Modem/Mode Control
R/W
05h
LSR Link Status
RO
06h
MSR Modem Status
RO
07h SPR/ASCR Scratchpad/Auxiliary Status and Control
R/W
Note 1. When bit 7 of this Register is set to 1, bits 6-0 of BSR select the bank,
as shown in Table 49.
Table 49. Bank Selection Encoding
BSR Bits
76543210
0xxxxxxx
10xxxxxx
11xxxx1x
11xxxxx1
11100000
11100100
11101000
11101100
11110000
11110100
Bank
Selected
Functionality
0
1
1
UART + IR
1
(SP1 + SP2)
2
3
4
5
IR Only
6
(SP2)
7
Table 50. Bank 1 Register Map
Offset Mnemonic
Register Name
Type
00h
LBGD(L) Legacy Baud Generator Divisor Port (Low Byte) R/W
01h
LBGD(H) Legacy Baud Generator Divisor Port (High Byte) R/W
02h
Reserved
03h LCR/BSR Line Control/Bank Select
R/W
04h - 07h
Reserved
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