PC87360 Datasheet, PDF (10/168 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Protection and Extensive GPIO Support

Table of Contents (Continued)
8.2.8
8.2.9
Master Bus Stall ........................................................................................................ 131
Repeated Start .......................................................................................................... 131
Master Error Detection .............................................................................................. 131
Bus Idle Error Recovery ............................................................................................ 131
Slave Mode ................................................................................................................ 132
Slave Receive and Transmit ...................................................................................... 132
Slave Bus Stall .......................................................................................................... 132
Slave Error Detection ................................................................................................ 132
Configuration ............................................................................................................. 132
SDA and SCL Signals ............................................................................................... 132
ACB Clock Frequency ............................................................................................... 132
8.3 ACB REGISTERS .................................................................................................................... 133
8.3.1 ACB Register Map ..................................................................................................... 133
8.3.2 ACB Serial Data Register (ACBSDA) ........................................................................ 133
8.3.3 ACB Status Register (ACBST) .................................................................................. 134
8.3.4 ACB Control Status Register (ACBCST) ................................................................... 135
8.3.5 ACB Control Register 1 (ACBCTL1) .......................................................................... 136
8.3.6 ACB Own Address Register (ACBADDR) ................................................................. 137
8.3.7 ACB Control Register 2 (ACBCTL2) .......................................................................... 137
8.4 ACB REGISTER BITMAP ........................................................................................................ 138
9.0 Legacy Functional Blocks
9.1 KEYBOARD AND MOUSE CONTROLLER (KBC) .................................................................. 140
9.1.1 General Description ................................................................................................... 140
9.1.2 KBC Register Map ..................................................................................................... 140
9.1.3 KBC Bitmap Summary ............................................................................................... 140
9.2 FLOPPY DISK CONTROLLER (FDC) ..................................................................................... 141
9.2.1 General Description ................................................................................................... 141
9.2.2 FDC Register Map ..................................................................................................... 141
9.2.3 FDC Bitmap Summary ............................................................................................... 142
9.3 PARALLEL PORT .................................................................................................................... 143
9.3.1 General Description ................................................................................................... 143
9.3.2 Parallel Port Register Map ......................................................................................... 143
9.3.3 Parallel Port Bitmap Summary .................................................................................. 144
9.4 UART FUNCTIONALITY (SP1 AND SP2) ............................................................................... 146
9.4.1 General Description ................................................................................................... 146
9.4.2 UART Mode Register Bank Overview ....................................................................... 146
9.4.3 SP1 and SP2 Register Maps for UART Functionality ................................................ 147
9.4.4 SP1 and SP2 Bitmap Summary for UART Functionality ........................................... 149
9.5 IR FUNCTIONALITY (SP2) ..................................................................................................... 151
9.5.1 General Description ................................................................................................... 151
9.5.2 IR Mode Register Bank Overview ............................................................................. 151
9.5.3 SP2 Register Map for IR Functionality ...................................................................... 152
9.5.4 SP2 Bitmap Summary for IR Functionality ................................................................ 153
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