NSAM265SR Datasheet, PDF (41/58 Pages) National Semiconductor (TI) – CompactSPEECH Digital Speech Processors

Appendix A Device Specifications (Continued)
A 4 3 TIMING DIAGRAMS
TL EE 12378 – 26
Note 1 This cycle may be either TI (Idle) or T1 of any non-DRAM bus cycle If the next bus cycle is to DRAM T3 is followed by three TI (Idle) cycles
Note 2 An external device can drive data from T2W3 to T3
Note 3 An external device can not drive data from T1 to T2W3
FIGURE A-10 DRAM Read Cycle Timing (NSAM265SR only)
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