NSAM265SR Datasheet, PDF (15/58 Pages) National Semiconductor (TI) – CompactSPEECH Digital Speech Processors

2 0 Functional Description (Continued)
In Normal Operation Mode
In normal operation mode a refresh bus cycle starts at
T2W1RF by asserting CAS (0) DWE stays inactive (1)
throughout the transaction Nine cycles follow the T2W1RF
cycle T2W2RF T2W3RF six T2WRF cycles and a T2 cy-
cle The RAS signal is asserted (0) at the first T2WRF cycle
The transaction is terminated at T3RF when RAS and CAS
signals become inactive (1) To ensure enough DRAM pre-
charge time the DRAM refresh bus cycle is separated by at
least three clock cycles from any other DRAM bus cycle
(read write or refresh) Other bus cycles can be performed
in parallel with a refresh transaction and or the three cycles
following the refresh transaction
In Power-Down Mode
In power-down mode a DRAM refresh cycle starts when the
CAS signal is held asserted (0) for 32 oscillator cycles RAS
is asserted (0) 16 oscillator cycles after the CAS signal is
asserted (0) After another 16 oscillator cycles both the RAS
and CAS signals become inactive (1) In power-down mode
DWE stays inactive (1)
In power-down mode A(0 10) and RA11 stay inactive (0)
and D(0 1) and D(3 7) are in TRI-STATE
2 6 DRAM ARAM SPECIFICATIONS (NSAM265SR)
The NSAM265SR supports three types of ARAM devices
 1M x 4 bits organized in 1024 rows x 1024 columns
 4M x 4 bits organized in 4096 rows x 1024 columns
 4M x 4 bits organized in 2048 rows x 2048 columns
ARAM Device
Type
4 Mbits
16 Mbits
16 Mbits
Number of
Rows
1024
4096
2048
Clean
Rows
4 (0 to 3)
16 (0 to 15)
4 (0 to 3)
Bad Nibbles in
One Row
k0 5%
k0 5%
k0 5%
 Clean rows are ARAM rows without any defects
 An ARAM row containing more bad nibbles than allowed
is counted as a bad row
 A nibble which contains one or more bad bits is counted
as one bad nibble
 The maximum number of bad rows permitted is 200
When the AMAP 3 command is issued and there are
more than 200 bad rows the ERR ARAM bit in the er-
ror word is set
2 7 DRAM ARAM CONFIGURATIONS (NSAM265SR)
During power-up the NSAM265SR automatically determines
the memory configuration used for message storage The
AMAP command returns the number of ARAMs
The following memory configurations are recognized
Number of Number of
ARAMs Messages
Data
Pins
Number of
Address Lines
ROWS x COLS
Address
Lines
1 (4 Mbits)
2 (4 Mbits)
1 (16 Mbits)
2 (16 Mbits)
1 (16 Mbits)
2 (16 Mbits)
100
400
400
1600
200
800
D0 – D3
D0 – D7
D0 – D3
D0 – D7
D0 – D3
D0 – D7
10 x 10
10 x 10
12 x 10
12 x 10
11 x 11
11 x 11
A0 – A9
A0 – A9
A0 – A10 RA11
A0 – A10 RA11
A0 – A10
A0 – A10
FIGURE 2-5 Connections for Two 1-Mbit c 4 ARAMs
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