NSAM265SR Datasheet, PDF (36/58 Pages) National Semiconductor (TI) – CompactSPEECH Digital Speech Processors

Appendix A Device Specifications (Continued)
A 4 SWITCHING CHARACTERISTICS
A 4 1 DEFINITIONS
All timing specifications in this section refer to 0 8V or 2 0V
on the rising or falling edges of the signals as illustrated in
Figures A-3 through A-10 unless specifically stated other-
wise
Maximum times assume capacitive loading of 50 pF
CLKIN crystal frequency is 40 96 MHz
Note CTTL is an internal signal and is used as a reference to explain the
timing of other signals See Figure A-21
Signal valid active or inactive time after a rising edge of CTTL or MWCLK
FIGURE A-3 Synchronous Output Signals (Valid Active and Inactive)
TL EE 12378 – 19
Signal valid time after a falling edge of MWCLK
FIGURE A-4 Synchronous Output Signals (Valid)
TL EE 12378 – 20
Signal hold time after a rising edge of CTTL
FIGURE A-5 Synchronous Output Signals (Hold)
TL EE 12378 – 21
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