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NSAM265SR Datasheet, PDF (40/58 Pages) National Semiconductor (TI) – CompactSPEECH Digital Speech Processors
Appendix A Device Specifications (Continued)
TABLE A-2 Timing for Output Signals (Continued)
Symbol Figure
Description
Reference Conditions
Min (ns)
tRASh
A-10
RAS Hold
After R E CTTL
tRASia
A-10
RAS Inactive
After R E CTTL T3 or T3RF
tRASLw
A-13
DRAM PDM RAS Width
At 0 8V Both Edges
tRLCL
A-13
DRAM PDM RAS Low after CAS Low F E CAS to F E RAS
tWRa
A-17
WR0 Active
After R E CTTL T1
tWRCSh
A-17
WR0 Hold after EMCS (Note B)
R E EMCS R E to R E WR0
tWRh
A-17
WR0 Hold
After R E CTTL
tWRia
A-17
WR0 Inactive
After R E CTTL T3
Note A In normal operation tCTp must be 48 8 ns in power-down mode tCTp must be 50 000 ns
Note B Guaranteed by design but not fully tested
00
200 0
200 0
10 0
tCTp 2 b 6
Symbol
Figure
Table A-3 Input Signals
Description
Reference Conditions
tCDIh
tCDIs
tDIh
tDIs
tMWCKh
tMWCKI
tMWCKp
tMWCLKh
tMWCLKs
tMWCSh
tMWCSs
tMWDIh
tMWDIs
tPWR
tRSTw
tXh
tXI
tXp
A-14
A-14
A-10
A-10
A-18
A-18
A-18
A-18
A-18
A-18
A-18
A-18
A-18
A-23
A-22
A-21
A-21
A-21
CDIN Hold
CDIN Setup
Data in Hold (D0 7)
Data in Setup (D0 7)
MICROWIRE Clock High (Slave)
MICROWIRE Clock Low (Slave)
MICROWIRE Clock Period (Slave) (Note A)
MWCLK Hold
MWCLK Setup
MWCS Hold
MWCS Setup
MWDIN Hold
MWDIN Setup
Power Stable to RESET R E (Note B)
RESET Pulse Width
CLKIN High
CLKIN Low
CLKIN Clock Period
Note A Guaranteed by design but not fully tested in power-down mode
Note B Guaranteed by design but not fully tested
After R E CTTL
Before R E CTTL
After R E CTTL T1 T3 or TI
Before R E CTTL T1 T3 or TI
At 2 0V (Both Edges)
At 0 8V (Both Edges)
R E MWCLK to next R E MWCLK
After MWCS becomes Inactive
Before MWCS becomes Active
After F E MWCLK
Before R E MWCLK
After R E MWCLK
Before R E MWCLK
After VCC reaches 4 5V
At 0 8V (Both Edges)
At 2 0V (Both Edges)
At 0 8V (Both Edges)
R E CLKIN to next R E CLKIN
Max (ns)
12 0
tCTp 2 a12
tCTp 2 a 12
Min (ns)
00
11 0
00
15 0
100 0
100 0
2 5 ms
50 0
100
50 0
100 0
50 0
100 0
30 ms
10 ms
tX1p 2 b 5
tX1p 2 b 5
24 4
40