NSAM265SR Datasheet, PDF (14/58 Pages) National Semiconductor (TI) – CompactSPEECH Digital Speech Processors

2 0 Functional Description (Continued)
FIGURE 2-3 Codec Protocol - Short Frame
TL EE 12378 – 6
FIGURE 2-4 Codec Protocol - Long Frame
TL EE 12378 – 7
2 5 DRAM ARAM Access (NSAM265SR)
Reading from DRAM
A read bus cycle starts at T1 when the row address is driv-
en on the address bus and the data bus is in TRI-STATE
DWE is inactive (1) throughout the bus cycle One idle cycle
(TI) is guaranteed before a DRAM bus cycle
In the next clock cycle (T2W1) RAS is asserted (0) T2W2
and T2W3 follow the T2W1 bus cycle At T2W3 the column
address is driven onto the address bus A(0 10) (RA11 is in
TRI-STATE) Six T2W cycles and one T2 cycle follow At the
first T2W cycle the CAS signal is asserted (0) At the end of
T2 the NSAM265SR samples the data
The bus cycle is terminated with a T3 cycle when RAS and
CAS signals become inactive (1) To ensure enough DRAM
pre-charge time the DRAM read bus cycle is separated by
at least three clock cycles from any other DRAM bus cycle
(read write or refresh) Other bus cycles can start after at
least one TI (Idle) cycle
For more details refer to the timing diagram Figure A-10
and AC DC specifications in ELECTRICAL CHARACTERIS-
TICS
Writing to DRAM
A write bus cycle starts at T1 when the row address is
driven on the address bus and the data bus is in TRI-
STATE One idle cycle (TI) is guaranteed before a DRAM
bus cycle
In the next clock cycle (T2W1) RAS is asserted (0) and the
data is available on the data bus (except for D2) T2W2 and
T2W3 follow the T2W1 cycle At T2W2 DWE is asserted (0)
to indicate the write operation
In the next cycle (T2W3) the column address is driven onto
the address bus A(0 10) and RA11 Then six T2W cycles
and one T2 cycle follow At the first T2W cycle CAS is
asserted (0)
The bus cycle is terminated by a T3 cycle when DWE RAS
and CAS signals become inactive (1) To provide enough
DRAM pre-charge time the DRAM write bus cycle is sepa-
rated by at least three clock cycles from any other DRAM
bus cycle (read write or refresh) Other bus cycles can start
after at least one TI cycle
For more details refer to the timing diagram Figure A-11
and AC DC specifications in ELECTRICAL CHARACTERIS-
TICS
2 5 1 Refreshing a DRAM ARAM
The NSAM265SR generates DRAM refresh bus cycles in
both normal operation and power-down modes In both cas-
es a clock generated by the clock generator sets the re-
fresh rate to of the oscillator frequency
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