COP404C Datasheet, PDF (4/18 Pages) National Semiconductor (TI) – COP404C ROMless CMOS Microcontrollers

Connection Diagram
Dual-In-Line Package
TL DD 5530–2
Order Number COP404CN
See NS Package Number N48A
Pin Descriptions
Pin
V_CC
V_SS
CKI
RS
CKOI
LL
GG
DD
D
IN IN
SO
SI
SK
IP IP
AAA
SKIP
AD DATA
MB
CKOH
DUAL
TIN
SEL
SEL
UNUSED
Description
Most positive voltage
Ground
Clock input
Reset input
General purpose input
TRI STATE I O
general purpose I O
general purpose outputs
Either general purpose output
or Dual Clock RC input
general purpose inputs
Serial data output
Serial data input
Serial data clock output
I O for ROM address and data
address outputs
Skip status output
Clock output
MICROBUS select input
Halt I O pin
Dual Clock select input
Timer input select pin should be
connected to GND
COP C emulation select input
COP C emulation select input
Ground
FIGURE 2
The internal architecture is shown in Figure 1 Data paths
are illustrated in simplified form to depict how the various
logic elements communicate with each other in implement-
ing the instruction set of the device Positive logic is used
When a bit is set it is a logic ‘‘1’’ when a bit is reset it is a
logic ‘‘0’’
PROGRAM MEMORY
Program Memory consists of a 2048-byte external memory
(typically PROM) Words of this memory may be program
instructions constants or ROM addressing data
ROM addressing is accomplished by a 11-bit PC register
which selects one of the 8-bit words contained in ROM A
new address is loaded into the PC register during each in-
struction cycle Unless the instruction is a transfer of control
instruction the PC register is loaded with the next sequen-
tial 11-bit binary count value
Three levels of subroutine nesting are implemented by a
three level deep stack Each subroutine call or interrupt
pushes the next PC address into the stack Each return
pops the stack back into the PC register
DATA MEMORY
Data memory consists of a 512-bit RAM organized as 8
data registers of 16 c 4-bit digits RAM addressing is imple-
mented by a 7-bit B register whose upper 3 bits (B_r) select 1
of 8 data registers and lower 4 bits (B_d) select 1 of 16 4-bit
digits in the selected data register While the 4-bit contents
of the selected RAM digit (M) are usually loaded into or
from or exchanged with the A register (accumulator) it
may also be loaded into or from the Q latches or T counter
or loaded from the L ports RAM addressing may also be
performed directly by the LDD and XAD instructions based
upon the immediate operand field of these instructions The
B_d register also serves as a source register for 4-bit data
sent directly to the D outputs
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