COP404C Datasheet, PDF (10/18 Pages) National Semiconductor (TI) – COP404C ROMless CMOS Microcontrollers

External Memory Interface
The COP404C is designed for use with an external Program
Memory
This memory may be implemented using any devices having
the following characteristics
1 random addressing
2 LSTTL or CMOS-compatible TRI-STATE outputs
3 LSTTL or CMOS-compatible inputs
4 access timee1 0 ms max
Typically these requirements are met using bipolar PROMs
or MOS CMOS PROMs EPROMs or E²PROMs
During operation the address of the next instruction is sent
out on A10 A9 A8 and IP7 through IP0 during the time that
AD DATA is high (logic ‘‘1’’eaddress mode) Address data
on the IP lines is stored into an external latch on the high-to-
low transition of the AD DATA line A10 A9 and A8 are
dedicated address outputs and do not need to be latched
When AD DATA is low (logic ‘‘0’’edata mode) the output
of the memory is gated onto IP7 through IP0 forming the
input bus Note that AD DATA output has a period of one
instruction time a duty cycle of approximately 50% and
specifies whether the IP lines are used for address output or
data input A simplified block diagram of the external memo-
ry interface is shown in Figure 11
TL DD 5530–13
FIGURE 11 External Memory Interface to COP404C
COP404C Instruction Set
Table II is a symbol table providing internal architecture in-
struction operand and operation symbols used in the in-
struction set table
Table III provides the mnemonic operand machine code
data flow skip conditions and description of each instruc-
tion
Table II Instruction Set Table Symbols
Symbol
Definition
Internal Architecture Symbols
A
4-bit Accumulator
B
7-bit RAM address register
Br
Upper 3 bits of B (register address)
Bd Lower 4 bits of B (digit address)
C
1-bit Carry register
D
4-bit Data output port
EN 4-bit Enable register
G
4-bit General purpose I O port
IL
two 1-bit (IN0 and IN3) latches
IN
4-bit input port
L
8-bit TRI-STATE I O port
M
4-bit contents of RAM addressed by B
PC 11-bit ROM address program counter
Q
8-bit latch for L port
SA 11-bit Subroutine Save Register A
SB 11-bit Subroutine Save Register B
SC 11-bit Subroutine Save Register C
SIO 4-bit Shift register and counter
SK Logic-controlled clock output
SKL 1-bit latch for SK output
T
8-bit timer
Instruction operand symbols
d
4-bit operand field 0 – 15 binary (RAM digit select)
r
3-bit operand field 0 – 7 binary (RAM register select)
a
11-bit operand field 0 – 2047
y
4-bit operand field 0 – 15 (immediate data)
RAM(x) RAM addressed by variable x
ROM(x) ROM addressed by variable x
Operational Symbols
a
Plus
b
Minus
– ^l Replaces
k _– l _{is exchanged with}
e
Is equal to
b
A
one’s complement of A
Z
exclusive-or
range of values
10