COP404C Datasheet, PDF (3/18 Pages) National Semiconductor (TI) – COP404C ROMless CMOS Microcontrollers

COP404C
AC Electrical Characteristics 0 C^sT_A^s70 C unless otherwise specified
Parameter
Conditions
Min
Max
Units
Instruction Cycle
Time t_c
Operating CKI
Frequency
Duty Cycle Note
V_CC^t V
V^lV_CC^t V
V_CC^t V
V^lV_CC^t V
f e MHz
DC
ms
DC
ms
DC
MHz
DC
kHz
Rise Time Note
f e MHz external clock
ns
Fall Time Note
ns
Instruction Cycle
Re k V_CCe V
Time using D as a
Ce pF
ms
RC Oscillator Dual
Clock Input Note
INPUTS See Fig
t_SETUP
G Inputs
T_c a
ms
SI Input
* ^{IP Input}
All Others
V_CC^t
V
ms
ms
ms
t_HOLD
V_CC^t V
ms
V^lV_CC^t V
ms
OUTPUT
PROPAGATION DELAY
V_OUTe V C_Le pF R_Le K
IP IP A A SKIP
t_PD t_PD
V_CC^t V
ms
V^lV_CC^t V
ms
AD DATA
t_PD t_PD
V_CC^t V
ns
V^lV_CC^t V
ms
ALL OTHER OUTPUTS
t_PD t_PD
V_CC^l V
ms
V^lV_CC^t V
ms
MICROBUS TIMING
Read Operation Fig
C_Le pF V_CCe Vg
Chip select stable before RD bt_CSR
ns
Chip select hold time for RD bt_RCS
ns
RD pulse width bt_RR
ns
Data delay from RD bt_RD
ns
RD to data floating bt_DF Note
ns
Write Operation Fig
Chip select stable before WR bt_CSW
ns
Chip select hold time for WR bt_WCS
ns
WR pulse width bt_WW
ns
Data set up time for WR bt_DW
ns
Data hold time for WR bt_WD
ns
INTR transition time from WR bt_WI
ns
Note 1 Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI and all other pins pulled up to V_CC with 20k resistors See
current drain equation on page 16
Note 2 Test conditions All inputs tied to V_CC L lines in TRI-STATE mode and tied to Ground all outputs tied to Ground
Note 3 When forcing HALT current is only needed for a short time (approx 200 ns) to flip the HALT flip-flop
Note 4 This parameter is only sampled and not 100% tested Variation due to the device included
Note 5 Voltage change must be less than 0 1 V_CC in a 1 ms period
Note 6 SO output sink current must be limited to keep V_OL less than 0 2 V_CC to prevent entering test mode
Note 7 MB TIN DUAL SEL10 SEL20 input levels at V_CC or V_SS
3