COP404C Datasheet, PDF (12/18 Pages) National Semiconductor (TI) – COP404C ROMless CMOS Microcontrollers

Instruction Set (Continued)
TABLE III COP404C Instruction Set (Continued)
Mnemonic
SMB
STII
X
XAD
XDS
XIS
Operand
0
1
2
3
y
r
rd
r
r
Hex
Code
4D
47
46
4B
7b
b6
23
b7
b4
Machine
Language
Code
(Binary)
l⁰¹⁰⁰l¹¹⁰¹l
l⁰¹⁰⁰l⁰¹¹¹l
l⁰¹⁰⁰l⁰¹¹⁰l
l⁰¹⁰⁰l¹⁰¹¹l
l⁰¹¹¹l ^y l
l⁰⁰l ^r l⁰¹¹⁰l
(re0 3)
l⁰⁰¹⁰l⁰⁰¹¹l
l¹l ^r l ^d l
l⁰⁰l ^r l⁰¹¹¹l
(re0 3)
l⁰⁰l ^r l⁰¹⁰⁰l
(re0 3)
Data Flow
x 1
RAM(B)₀
x 1
RAM(B)₁
x 1
RAM(B)₂
x 1
RAM(B)₃
y x RAM(B)
Bd a 1 x Bd
RAM(B)
A
x Br Z r
Br
RAM(r d)
A
RAM(B)
A
Bdb1 x Bd
x Br Z r
Br
RAM(B)
A
Bda1 x Bd
x Br Z r
Br
Skip
Conditions
None
None
None
None
Bd
decrements
past 0
Bd
increments
past 15
Description
Set RAM Bit
Store Memory Immediate
and Increment Bd
Exchange RAM with A
Exclusive-OR Br with r
Exchange A with RAM
pointed to directly by r d
Exchange RAM with A
and Decrement Bd
Exclusive-OR Br with r
Exchange RAM with A
and Increment Bd
Exclusive-OR Br with r
REGISTER REFERENCE INSTRUCTIONS
CAB
CBA
LBI
LEI
XABR
50
l⁰¹⁰¹l⁰⁰⁰⁰l
4E
l⁰¹⁰⁰l¹¹¹⁰l
rd
l⁰⁰l ^r l^(d-1)l
(re0 3
de0 9 15)
or
33
l⁰⁰¹¹l⁰⁰¹¹l
l¹l ^r l ^d l
(any r any d)
y
33
l⁰⁰¹¹l⁰⁰¹¹l
6b _l0110_l y _l
12
l⁰⁰⁰¹l⁰⁰¹⁰l
A x Bd
Bd x A
rdxB
y x EN
A
Br
None
None
Skip until
not a LBI
Copy A to Bd
Copy Bd to A
Load B Immediate with r d
(Note 5)
None
None
Load EN Immediate (Note 6)
Exchange A with Br (Note 7)
TEST INSTRUCTIONS
SKC
SKE
SKGZ
SKGBZ
0
1
2
3
SKMBZ
0
1
2
3
SKT
20
l⁰⁰¹⁰l⁰⁰⁰⁰l
21
l⁰⁰¹⁰l⁰⁰⁰¹l
33
l⁰⁰¹¹l⁰⁰¹¹l
21
l⁰⁰¹⁰l⁰⁰⁰¹l
33
l⁰⁰¹¹l⁰⁰¹¹l
1st byte
01
l⁰⁰⁰⁰l⁰⁰⁰¹l
11
03
l⁰⁰⁰¹l⁰⁰⁰¹l
l⁰⁰⁰⁰l⁰⁰¹¹l
2nd byte
13
l⁰⁰⁰¹l⁰⁰¹¹l
01
l⁰⁰⁰⁰l⁰⁰⁰¹l
11
l⁰⁰⁰¹l⁰⁰⁰¹l
03
l⁰⁰⁰⁰l⁰⁰¹¹l
13
l⁰⁰⁰¹l⁰⁰¹¹l
41
l⁰¹⁰⁰l⁰⁰⁰¹l
Ce‘‘1’’
AeRAM(B)
G_{3 0}e0
G₀e0
G₁e0
G₂e0
G₃e0
RAM(B)₀e0
RAM(B)₁e0
RAM(B)₂e0
RAM(B)₃e0
A time-base
counter
carry has
occured
since last test
Skip if C is True
Skip if A Equals RAM
Skip if G is Zero
(all 4 bits)
Skip if G Bit is Zero
Skip if RAM Bit is Zero
Skip on Timer
(Note 2)
12