COP404C Datasheet, PDF (1/18 Pages) National Semiconductor (TI) – COP404C ROMless CMOS Microcontrollers

April 1992
COP404C ROMless CMOS Microcontrollers
General Description
The COP404C ROMless Microcontroller is a member of the
COPS^TM family fabricated using double-poly silicon gate
CMOS (microCMOS) technology The COP404C contains
CPU RAM I O and is identical to a COP444C device ex-
cept the ROM has been removed and pins have been add-
ed to output the ROM address and to input the ROM data
The COP404C can be configured by means of external
pins to function as a COP444C a COP424C or a
COP410C Pins have been added to allow the user to select
the various functional options that are available on the fami-
ly of mask-programmed CMOS parts The COP404C is pri-
marily intended for use in the development and debug of a
COP program for the COP444C 445C COP424C 425C
and COP410C 411C devices prior to masking the final part
The COP404C is also appropriate in low volume applica-
tions or when the program might be changing
MICROBUSTM and MICROWIRETM are trademarks of National Semiconductor Corporation
TRI-STATE is a registered trademark of National Semiconductor Corporation
Block Diagram
Features
Y _{Accurate emulation of the COP444C COP424C and}
COP410C
Y _{Lowest Power Dissipation (50 mW typical)}
Y _{Fully static (can turn off the clock)}
Y _{Power saving IDLE state and HALT mode}
Y _{4 ms instruction time plus software selectable clocks}
Y ₁₂₈ c _{4 RAM addresses 2k} c _{8 ROM}
Y _{True vectored interrupt plus restart}
Y _{Three-level subroutine stack}
Y _{Single supply operation (2 4V to 5 5V)}
Y _{Programmable read write 8-bit timer event counter}
Y _{Internal binary counter register with MICROWIRE}TM
serial I O capability
Y _{General purpose and TRI-STATE outputs}
Y _{LSTTL CMOS compatible}
Y _MICROBUSTM _compatible
Y _{Software hardware compatible with other members of}
the COP400 family
C1995 National Semiconductor Corporation TL DD 5530
FIGURE 1 Block Diagram
TL DD 5530 – 1
RRD-B30M105 Printed in U S A