LP3906 Datasheet, PDF (37/38 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

Thermal Performance of the LLP
Package
The LP3906 is a monolithic device with integrated power
FETs. For that reason, it is important to pay special attention
to the thermal impedance of the LLP package and to the
PCB layout rules in order to maximize power dissipation of
the LLP package.
The LLP package is designed for enhanced thermal perfor-
mance and features an exposed die attach pad at the bottom
center of the package that creates a direct path to the PCB
for maximum power dissipation. Compared to the traditional
leaded packages where the die attach pad is embedded
inside the molding compound, the LLP reduces one layer in
the thermal path.
The thermal advantage of the LLP package is fully realized
only when the exposed die attach pad is soldered down to a
thermal land on the PCB board with thermal vias planted
underneath the thermal land. Based on thermal analysis of
the LLP package, the junction-to-ambient thermal resistance
(θJA) can be improved by a factor of two when the die attach
pad of the LLP package is soldered directly onto the PCB
with thermal land and thermal vias, as opposed to an alter-
native with no direct soldering to a thermal land. Typical pitch
and outer diameter for thermal vias are 1.27mm and 0.33mm
respectively. Typical copper via barrel plating is 1oz, al-
though thicker copper may be used to further improve ther-
mal performance. The LP3906 die attach pad is connected
to the substrate of the IC and therefore, the thermal land and
vias on the PCB board need to be connected to ground
(GND pin).
For more information on board layout techniques, refer to
Application Note AN–1187 “Leadless Lead frame Package
(LLP).” on http://www.national.com This application note also
discusses package handling, solder stencil and the assem-
bly process.
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