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LP3906 Datasheet, PDF (34/38 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface
Application Notes (Continued)
Voltage peak-to-peak ripple due to ESR can be expressed
as follows:
VPP–ESR = 2 x IRIPPLE x RESR
Because the VPP-C and VPP-ESR are out of phase, the rms
value can be used to get an approximate value of the peak-
to-peak ripple:
Note that the output voltage ripple is dependent on the
inductor current ripple and the equivalent series resistance
of the output capacitor (RESR). The RESR is frequency de-
pendent as well as temperature dependent. The RESR
should be calculated with the applicable switching frequency
and ambient temperature.
Min
Recommended
Capacitor
Unit Description
Value
Type
CLDO1
LDO1 output Ceramic, 6.3V,
0.47 µF
capacitor
X5R
CLDO2
0.47 µF LDO2 output Ceramic, 6.3V,
capacitor
X5R
CSW1
10.0 µF SW1 output Ceramic, 6.3V,
capacitor
X5R
CSW2
10.0 µF SW2 output Ceramic, 6.3V,
capacitor
X5R
I2C Pullup Resistor
Both I2C_SDA and I2C_SCL terminals need to have pullup
resistors connected to VINLDO12 or to the power supply of
the I2C master. The values of the pull-up resistors (typ.
∼1.8kΩ) are determined by the capacitance of the bus. Too
large of a resistor combined with a given bus capacitance
will result in a rise time that would violate the max. rise time
specification. A too small resistor will result in a contention
with the pull-down transistor on either slave(s) or master.
Operation without I2C Interface
Operation of the LP3906 without the I2C interface is possible
if the system can operate with default values for the LDO and
Buck regulators. (Read below: Factory programmable op-
tions). The I2C-less system must rely on the correct default
output values of the LDO and Buck converters.
Factory Programmable Options
The following options are EPROM programmed during final
test of the LP3906. The system designer that needs specific
options is advised to contact the local National Semiconduc-
tor sales office.
Factory programmable options
Enable delay for power on
SW1 ramp speed
SW2 ramp speed
Current value
code 010 (see
Control 1 register
section)
8 mV/µs
8 mV/µs
The I2C Chip ID address is offered as a metal mask option.
The current value equals 0x60.
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