LP3906 Datasheet, PDF (24/38 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

LP3906 Control Registers (Continued)
INTERRUPT STATUS REGISTER (ISRA) 0X02
This register informs the user of the temperature status of the chip.
Name
Access
Data
Reset
D7-2
—
—
Reserved
0
D1
Temp 125˚C
R
Status bit for thermal warning PMIC T>125˚C
0 – PMIC Temp. < 125˚C
1 – PMIC Temp. > 125˚C
0
D0
—
—
Reserved
0
CONTROL 1 REGISTER (SCR1) 0X07
This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM and PWM mode
for the bucks, and also to select between an internal and external clock for the bucks.
The external LDO and SW enables should be pulled LOW to allow the blocks to sequence correctly through assertion of the EN_T
pin.
D7
Name —
Access —
Data Reserved
Reset 0
D6-4
D3
EN_DLY
—
R/W
—
Selects the preset Reserved
delay sequence from
EN_T assertion
(shown below)
010
1
D2
FPWM2
R/W
Buck 2 PWM /PFM
Mode select
0 – Auto Switch PFM
- PWM operation
1 – PWM Mode Only
0
D1
FPWM1
R/W
Buck 1 PWM /PFM
Mode select
0 – Auto Switch PFM
- PWM operation
1 – PWM Mode Only
0
D0
ECEN
R/W
External Buck Clock
Select
0 – Internal 2 MHz
Oscillator clock
1 – External 13 MHz
Oscillator clock
0
EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION
EN_DLY<2:0>
000
001
010
011
100
101
110
111
Buck1
1
1
1.5
1.5
1.5
1.5
3
2
Delay (ms)
Buck2
1
1.5
2
2
2
1.5
2
3
LDO1
1
2
3
1
3
2
1
6
LDO2
1
2
6
1
6
2
1.5
11
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