LP3906 Datasheet, PDF (35/38 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

Application Notes (Continued)
MODE BOUNCE
PFM-PWM transition at low load current.
To improve efficiency at lower load currents LP3906 buck
converters employ an automatically invoked PFM mode for
the low load operation. The PFM mode operates with a much
lower value quiescent current (I_Q) than the PWM mode of
operation that is used in the higher load currents.
As shown in the datasheet section about SW operation,
there is a DC voltage difference between the two modes of
operation, with Vout PFM being typically 1.2% higher than
Vout PWM. So there is a DC voltage level transition and
some associated dynamic perturbation at the mode transi-
tion point.
The transition between the two modes of operation has an
associated hysterisis in the transition current value, That is,
the transition point for increasing current (PFM to PWM) is at
a higher value that the decreasing current (PWM to PFM).
This hysterisis is to ensure that in the event that the load
current values equals the PFM PWM transition value, the
device will not make multiple transitions between modes;
this reduces the noise at this load by eliminating multiple
transitions between modes (also known as mode bounce).
Under some conditions of high Vin and Low Vout the hyster-
sis value is reduced and some amount of mode bounce can
occur. Under these conditions, the regulator still maintains
DC regulation, however the output ripple is more pro-
nounced. Refer to the attached Vout vs Vin chart below that
shows the operational area that may exhibit this increased
output ripple. If the application is expected to be operated in
the area of concern AND have a static load current of the
transition current value, the user can avoid the possible
noise increase by invoking the components’ “Force PWM
mode”.
LP3906 Buck Converter
V_OUT vs V_IN Operating Range
during PFM-PWM-PPM Transition
20197865
35
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