LP3906 Datasheet, PDF (15/38 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

DC/DC Converters
OVERVIEW
The LP3906 supplies the various power needs of the application by means of two Linear Low Drop Regulators LDO1 and LDO2
and two Buck converters SW1 and SW2. The table here under lists the output characteristics of the various regulators.
SUPPLY SPECIFICATION
Supply
Load
V_OUT Range(V)
Output
Resolution (mV)
LDO1
analog
1.0 to 3.5
100
LDO2
analog
1.0 to 3.5
100
SW1
digital
0.8 to 2.0
50
SW2
digital
1.0 to 3.5
100
*For default values of the regulators, please consult Default Voltage Options Table page 3
I_MAX
Maximum Output
Current (mA)
300
300
1500
1500
LINEAR LOW DROP-OUT REGULATORS (LDOS)
LDO1 and LDO2 are identical linear regulators targeting
analog loads characterized by low noise requirements.
LDO1 and LDO2 are enabled through the ENLDO pin or
through the corresponding LDO1 or LDO2 control register.
The output voltages of both LDOs are register program-
mable. The default output voltages are factory programmed
during Final Test, which can be tailored to the specific needs
of the system designer.
NO-LOAD STABILITY
The LDOs will remain stable and in regulation with no exter-
nal load. This is an important consideration in some circuits,
for example CMOS RAM keep-alive applications.
LDO1 AND LDO2 CONTROL REGISTERS
LDO1 and LDO2 can be configured by means of the LDO1
and LDO2 control registers. The output voltage is program-
20197822
mable in steps of 100mV from 1.0V to 3.5V by programming
bits D4-0 in the LDO Control registers. Both LDO1 and LDO2
are enabled by applying a logic 1 to the ENLDO1 and
ENLDO2 pin. Enable/disable control is also provided through
enable bit of the LDO1 and LDO2 control registers. The
value of the enable LDO bit in the register is logic 1 by
default. The output voltage can be altered while the LDO is
enabled.
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