LP3906 Datasheet, PDF (21/38 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

I²C Compatible Serial Interface
I²C SIGNALS
The LP3906 features an I²C compatible serial interface,
using two dedicated pins: SCL and SDA for I²C clock and
data respectively. Both signals need a pull-up resistor ac-
cording to the I²C specification. The LP3906 interface is an
I²C slave that is clocked by the incoming SCL clock.
Signal timing specifications are according to the I²C bus
specification. The maximum bit rate is 400 kbit/s. See I²C
specification from Philips for further details.
I²C DATA VALIDITY
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL), e.g.- the state of the data
line can only be changed when CLK is LOW.
I²C Signals: Data Validity
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I²C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as the SDA
signal transitioning from HIGH to LOW while the SCL line is
HIGH. STOP condition is defined as the SDA transitioning
from LOW to HIGH while the SCL is HIGH. The I2C master
always generates START and STOP bits. The I2C bus is
considered to be busy after START condition and free after
STOP condition. During data transmission, I2C master can
generate repeated START conditions. First START and re-
peated START conditions are equivalent, function-wise.
START and STOP Conditions
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TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledged related clock pulse is generated by the mas-
ter. The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the 9th clock pulse, signifying acknowledge-
ment. A receiver which has been addressed must generate
an acknowledgement (“ACK”) after each byte has been re-
ceived.
After the START condition, the I2C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). Please note that
according to industry I2C standards for 7-bit addresses, the
MSB of an 8-bit address is removed, and communication
actually starts with the 7th most significant bit. For the eighth
bit (LSB), a “0” indicates a WRITE and a “1” indicates a
READ. The second byte selects the register to which the
data will be written. The third byte contains data to write to
the selected register.
LP3906 has a chip address of 60’h, which is factory
programmed.
I²C Chip Address
21
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