COP8ACC Datasheet, PDF(33/43 Page) National Semiconductor (TI) – 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k or 16k Memory and High Resolution A/D

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COP8ACC Datasheet, PDF (33/43 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k or 16k Memory and High Resolution A/D

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Addressing Modes (Continued)

Immediate

The instruction contains an 8-bit immediate field as the

operand.

Short Immediate

This addressing mode is used with the Load B Immediate

instruction. The instruction contains a 4-bit immediate field

as the operand.

Indirect

This addressing mode is used with the LAID instruction. The

contents of the accumulator are used as a partial address

(lower 8 bits of PC) for accessing a data operand from the

program memory.

TRANSFER OF CONTROL ADDRESSING MODES

Relative

This mode is used for the JP instruction, with the instruction

field being added to the program counter to get the new

program location. JP has a range from â31 to +32 to allow a

1-byte relative jump (JP + 1 is implemented by a NOP

instruction). There are no âpagesâ when using JP, since all 15

bits of PC are used.

Absolute

This mode is used with the JMP and JSR instructions, with

the instruction field of 12 bits replacing the lower 12 bits of

the program counter (PC). This allows jumping to any loca-

tion in the current 4k program memory segment.

Absolute Long

This mode is used with the JMPL and JSRL instructions, with

the instruction field of 15 bits replacing the entire 15 bits of

the program counter (PC). This allows jumping to any loca-

tion up to 32k in the program memory space.

Indirect

This mode is used with the JID instruction. The contents of

the accumulator are used as a partial address (lower 8 bits of

PC) for accessing a location in the program memory. The

contents of this program memory location serve as a partial

address (lower 8 bits of PC) for the jump to the next instruc-

tion.

INSTRUCTION SET

ADD

ADC

SUBC

AND

ANDSZ

XOR

IFEQ

IFNE

IFGT

IFBNE

DRSZ

A,Meml

A,Imm

A,Meml

MD,Imm

A,Meml

Reg

ADD

ADD with Carry

Subtract with Carry

Logical AND

Logical AND Immed., Skip if Zero

Logical OR

Logical EXclusive OR

IF EQual

IF Not Equal

IF Greater Than

If B Not Equal

Decrement Reg., Skip if Zero

Note: The VIS is a special case of the Indirect Transfer of Control addressing

mode, where the double byte vector associated with the interrupt is

transferred from adjacent addresses in the program memory into the

program counter (PC) in order to jump to the associated interrupt

service routine.

Instruction Set

GIE

[B]

[X]

Mem

Meml

Imm

Reg

Bit

Registers

8-Bit Accumulator Register

8-Bit Address Register

8-Bit Stack Pointer Register

15-Bit Program Counter Register

Upper 7 Bits of PC

Lower 8 Bits of PC

1-Bit of PSW Register for Carry

1-Bit of PSW Register for Half Carry

1-Bit of PSW Register for Global Interrupt

Enable

Interrupt Vector Upper Byte

Interrupt Vector Lower Byte

Symbols

Memory Indirectly Addressed by B Register

Memory Indirectly Addressed by X Register

Direct Addressed Memory

Direct Addressed Memory or [B]

Direct Addressed Memory or [B] or Immediate

Data

8-Bit Immediate Data

(Includes B, X and SP)

Bit Number (0 to 7)

Loaded with

Exchanged with

A â A + Meml

A â A + Meml + C, C â Carry, HC â Half Carry

A â A â MemI + C, C â Carry, HC â Half Carry

A â A and Meml

Skip next if (A and Imm) = 0

A â A or Meml

A â A xor Meml

Compare MD and Imm, Do next if MD = Imm

Compare A and Meml, Do next if A = Meml

Compare A and Meml, Do next if A â Meml

Compare A and Meml, Do next if A > Meml

Do next if lower 4 bits of B â Imm

Reg â Reg â 1, Skip if Reg = 0

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