COP8ACC Datasheet, PDF(16/43 Page) National Semiconductor (TI) – 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k or 16k Memory and High Resolution A/D

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COP8ACC Datasheet, PDF (16/43 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k or 16k Memory and High Resolution A/D

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Timers (Continued)

Mode 3. Input Capture Mode

The devices can precisely measure external frequencies or

time external events by placing the timer block, T1, in the

input capture mode.

In this mode, the timer T1 is constantly running at the fixed tC

rate. The two registers, R1A and R1B, act as capture regis-

ters. Each register acts in conjunction with a pin. The register

R1A acts in conjunction with the T1A pin and the register

R1B acts in conjunction with the T1B pin.

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin. Control bits,

T1C3, T1C2 and T1C1, allow the trigger events to be speci-

fied either as a positive or a negative edge. The trigger

condition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the T1A and T1B pins will be respectively latched into the

pending flags, T1PNDA and T1PNDB. The control flag

T1ENA allows the interrupt on T1A to be either enabled or

disabled. Setting the T1ENA flag enables interrupts to be

generated when the selected trigger condition occurs on the

T1A pin. Similarly, the flag T1ENB controls the interrupts

from the T1B pin.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer T1C0

pending flag (the T1C0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the T1C0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the T1ENA control flag. When a T1A interrupt

occurs in the Input Capture mode, the user must check both

the T1PNDA and T1C0 pending flags in order to determine

whether a T1A input capture or a timer underflow (or both)

caused the interrupt.

DS012865-59

FIGURE 11. Timer in Input Capture Mode

Figure 11 shows a block diagram of the timer in Input Cap-

ture mode.

TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

T1C3 Timer mode control

T1C2 Timer mode control

T1C1 Timer mode control

T1C0

Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in

Mode 3 (Input Capture)

T1PNDA Timer Interrupt Pending Flag

T1ENA Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

T1PNDB Timer Interrupt Pending Flag

T1ENB Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below:

Mode

T1C3

T1C2

T1C1

Description

PWM: T1A Toggle

PWM: No T1A

Toggle

External Event

Counter

External Event

Counter

Interrupt A

Source

Autoreload RA

Timer

Underflow

Timer

Underflow

Interrupt B

Source

Autoreload RB

Pos. T1B Edge

Timer

Counts On

Pos. T1A

Edge

Pos. T1A

Edge

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