COP8ACC Datasheet, PDF (13/43 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k or 16k Memory and High Resolution A/D

Oscillator Circuits (Continued)
RC > 5 x POWER SUPPLY RISE TIME
DS012865-53
FIGURE 6. Recommended Reset Circuit
Figure 7 shows the Crystal and R/C Oscillator diagrams.
DS012865-54
DS012865-55
FIGURE 7. Crystal and R/C Oscillator Diagrams
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
Table 1 shows the component values required for various
standard crystal values.
TABLE 1. Crystal Oscillator Configuration, T_A = 25˚C
R1 R2 C1
(kΩ) (MΩ) (pF)
C2 CKI Freq
Conditions
(pF)
(MHz)
0
1
30 30–36
10
V_CC = 5V
0
1
30 30–36
4
V_CC = 5V
0
1
200 100–150 0.455
V_CC = 5V
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart input.
Note: Use of the R/C oscillator option will result in higher electromagnetic
emissions.
Table 2 shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
TABLE 2. RC Oscillator Configuration, T_A = 25˚C
R
C
(kΩ) (pF)
CKI Freq
(MHz)
Instr. Cycle
Conditions
(µs)
3.3 82 2.2 to 2.7
5.6 100 1.1 to 1.3
6.8 100 0.9 to 1.1
3.7 to 4.6
7.4 to 9.0
8.8 to 10.8
V_CC = 5V
V_CC = 5V
V_CC = 5V
Note 18: 3k ≤ R ≤ 200k
Note 19: 50 pF ≤ C ≤ 200 pF
Control Registers
CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7
Bit 0
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
T1C3
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C1
Timer T1 mode control bit
T1C0
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
MSEL
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
IEDG
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
PSW Register (Address X'00EF)
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7
Bit 0
The PSW register contains the following select bits:
HC
Half Carry Flag
C
Carry Flag
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
EXPND External interrupt pending
BUSY MICROWIRE/PLUS busy shifting flag
EXEN Enable external interrupt
GIE
Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB
Bit 7
Bit 0
The ICNTRL register contains the following bits:
Reserved This bit is reserved and should be zero.
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