COP8ACC Datasheet, PDF (14/43 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k or 16k Memory and High Resolution A/D

Control Registers (Continued)
LPEN
T0PND
T0EN
µWPND
µWEN
T1PNDB
T1ENB
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
MICROWIRE/PLUS interrupt pending
Enable MICROWIRE/PLUS interrupt
Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
Timer T1 Interrupt Enable for T1B Input cap-
ture edge
Timers
The devices contain a very versatile set of timers (T0 and
T1). All timers and associated autoreload/capture registers
power up containing random data.
TIMER T0 (IDLE TIMER)
The devices support applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle clock, t_C. The user cannot read or
write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
• Exit out of the Idle Mode (See Idle Mode description)
• WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
Figure 8 is a functional block diagram showing the structure
of the IDLE Timer and its associated interrupt logic.
Bits 11 through 15 of the ITMR register can be selected for
triggering the IDLE Timer interrupt. Each time the selected
bit underflows (every 4k, 8k, 16k, 32k or 64k instruction
cycles), the IDLE Timer interrupt pending bit T0PND is set,
thus generating an interrupt (if enabled), and bit 6 of the Port
G data register is reset, thus causing an exit from the IDLE
mode if the devices are in that mode.
In order for an interrupt to be generated, the IDLE Timer
interrupt enable bit T0EN must be set, and the GIE (Global
Interrupt Enable) bit must also be set. The T0PND flag and
T0EN bit are bits 5 and 4 of the ICNTRL register, respec-
tively. The interrupt can be used for any purpose. Typically, it
is used to perform a task upon exit from the IDLE mode. For
more information on the IDLE mode, refer to the Power Save
Modes section.
The Idle Timer period is selected by bits 0–2 of the ITMR
register Bits 3–7 of the ITMR Register are reserved and
should not be used as software flags.
ITMR Register (Address X’0xCF)
Bit 7
Reserved
Bit 3
ITSEL2
ITSEL1
ITSEL0
Bit 0
TABLE 3. Idle Timer Window Length
ITSEL2 ITSEL1 ITSEL0
Idle Timer Period
(Instruction Cycles)
0
0
0
4,096
0
0
1
8,192
0
1
0
16,384
0
1
1
32,768
1
X
X
65,536
The ITMR register is cleared on Reset and the Idle Timer
period is reset to 4,096 instruction cycles.
Any time the IDLE Timer period is changed there is the
possibility of generating a spurious IDLE Timer interrupt by
setting the T0PND bit. The user is advised to disable IDLE
Timer interrupts prior to changing the value of the ITSEL bits
of the ITMR Register and then clear the T0PND bit before
attempting to synchronize operation to the IDLE Timer.
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DS012865-56
FIGURE 8. Functional Block Diagram for Idle Timer T0
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