COP8ACC Datasheet, PDF (17/43 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k or 16k Memory and High Resolution A/D

Timers (Continued)
Mode
3
T1C3
0
1
0
1
T1C2
1
1
1
1
T1C1
0
0
1
1
Description
Captures:
T1A Pos. Edge
T1B Pos. Edge
Captures:
T1A Pos. Edge
T1B Neg. Edge
Captures:
T1A Neg. Edge
T1B Neg. Edge
Captures:
T1A Neg. Edge
T1B Neg. Edge
Interrupt A
Source
Pos. T1A Edge
or Timer
Underflow
Pos. T1A
Edge or Timer
Underflow
Neg. T1A
Edge or Timer
Underflow
Neg. T1A
Edge or Timer
Underflow
Interrupt B
Source
Pos. T1B Edge
Neg. T1B
Edge
Neg. T1B
Edge
Neg. T1B
Edge
Timer
Counts On
t_C
t_C
t_C
t_C
HIGH SPEED CAPTURE TIMER
The devices provide a 16-bit high-speed capture timer. The
timer consists of a 16-bit up-counter that is clocked with the
device clock input frequency (CKI) and an 8-bit control reg-
ister. The 16-bit counter is mapped as two read/write 8-bit
registers. This timer is specifically designed to be used in
conjunction with the Analog Function Block (comparator,
analog multiplexer, constant current source) to implement a
low-cost, high-resolution, single-slope A/D.
The timer is automatically stopped in the event of a capture
to allow the software to read the timer value. Coming out of
reset the counter is disabled (stopped) and reads all “0”.
Setting the Capture Timer Run bit CAPRUN bit in the Cap-
ture Control Register (CAPCNTL) will start the counter. The
counter will count up until a capture event (negative edge) is
received. Upon a capture the counter will be stopped, the
Capture Pending bit (CAPPND) is set, and the CAPRUN bit
is automatically reset. If capture interrupts are enabled
(CAPIEN=1), the capture event will generate an interrupt.
Setting the CAPRUN bit again by software will start a new
counting cycle. If the Capture Mode bit is reset (CAP-
MOD=0) the capture timer will be automatically initialized to
all “0” with each setting of the CAPRUN bit. If CAPMOD=1
the timer will not be cleared when setting the CAPRUN bit,
thus allowing the user’s software to pre-load the timer reg-
isters with any desired value. This mode can be used in
conjunction with the timer’s overflow to implement for ex-
ample a programmable delay counter.
“CAPTURE MODE” is only active when the CAPRUN bit is
set, i.e. any capture events received while the timer is
stopped (CAPRUN=0) will be ignored and will not cause the
CAPPND bit to be set. The capture counter can also be
stopped (frozen) by the user’s software resetting the CA-
PRUN bit.
If the user program tries to set the CAPRUN bit at the same
time that the hardware gets a capture event and tries to reset
the CAPRUN bit, the hardware will have precedence.
Should the counter overflow before a capture condition oc-
curs, the Capture Overflow bit (CAPOVL) bit in the
CAPCNTL register will be set. If Capture interrupts are en-
abled (CAPIEN=1) an overflow will generate an interrupt.
The user software should reset this bit before the next
overflow occurs, otherwise subsequent overflow conditions
cannot be detected.
Capture Overflow interrupt and Capture Pending interrupt
share the same interrupt vector.
CAPCNTL Register (Address (X’CE)
Reserved CAPMOD CAPRUN CAPOVL CAPPND CAPIEN
Bit 7-5
Bit 4
Bit 0
The CAPCNTL register contains the following bits:
Reserved These bits are reserved and should must be
zero.
CAPMOD Reset Time.
0: reset timer to “0” when CAPRUN bit gets set
1: DO NOT reset timer to “0” when CAPRUN bit
gets set.
CAPRUN
Capture Timer Run. Setting this bit to one will
start the capture timer. This bit gets automatically
reset to “0” when a capture events occurs. Writ-
ing a “0” by software will also reset the bit and
stop the timer.
CAPOVL Capture Timer Overflow. Gets set to “1” upon
timer overflow. Has to be reset by user’s soft-
ware. If CAPIEN = 1 an interrupt is generated.
CAPPND Capture pending.
Gets automatically set when a capture event
occurs. If CAPIEN = 1 an interrupt is generated.
Has to be reset by the user’s software.
CAPIEN Capture Interrupt enable,
1 = enable interrupts, 0 = disable interrupts
Power Save Modes
The devices offer the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board os-
cillator circuitry and timer T0 are active but all other micro-
controller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
HALT MODE
The devices can be placed in the HALT mode by writing a “1”
to the HALT flag (G7 data bit). All microcontroller activities,
including the clock and timers, are stopped. The WATCH-
DOG logic on the devices is disabled during the HALT mode.
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