DS90C241_0608 Datasheet, PDF (3/21 Pages) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min Typ Max Units
LVDS DC SPECIFICATIONS
V_OD Output Differential Voltage R_L = 100Ω, w/o Pre-emphasis
(D_OUT+)– (D_OUT−)
VODSEL = L
(VODSEL = H) (Figure 16)
Tx: D_OUT+, D_OUT−
250 400 600 mV
(450) (750) (1200)
∆V_OD Output Differential Voltage
Unbalance
R_L = 100Ω, w/o Pre-emphasis
10 50 mV
V_OS
∆V_OS
I_OS
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
R_L = 100Ω, w/o Pre-emphasis
R_L = 100Ω, w/o Pre-emphasis
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = L
1.00 1.25 1.50 V
1 50 mV
−2
−8 mA
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = H
−7
−13 mA
I_OZ
TRI-STATE Output Current TPWDNB, DEN = 0V,
DOUT = 0V or 2.4V
−15 ±1 +15 µA
SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs
I_CCT Serializer (Tx)
Total Supply Current
(includes load current)
R_L = 100Ω
R_PRE = OFF
VODSEL = H/L
Checker-board pattern (Figure 1)
f = 35 MHz
40 65 mA
R_L = 100Ω
R_PRE = 6 kΩ
VODSEL = H/L
Checker-board pattern (Figure 1)
f = 35 MHz
45 70 mA
Serializer (Tx)
Total Supply Current
(includes load current)
R_L = 100Ω
R_PRE = OFF
VODSEL = H/L
f = 35 MHz
40 65 mA
R_L = 100Ω
R_PRE = 6 kΩ
VODSEL = H/L
Random pattern
f = 35 MHz
45 70 mA
I_CCTZ
Serializer (Tx)
TPWDNB = 0V
Supply Current Power-down (All other LVCMOS Inputs = 0V)
800 µA
I_CCR
Deserializer (Rx)
Total Supply Current
(includes load current)
C_L = 8 pF LVCMOS Output
Checker-board pattern
(Figure 2)
f = 35 MHz
75 mA
Deserializer (Rx)
Total Supply Current
(includes load current)
C_L = 8 pF LVCMOS Output
Random pattern
f = 35 MHz
50 mA
I_CCRZ
Deserializer (Rx)
Supply Current Power-down
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
R_IN+/ R_IN- = 0V)
50 µA
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t_TCP
t_TCIH
t_TCIL
t_CLKT
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
(Figure 6)
(Figure 5)
Min
28.6
0.4T
0.4T
Typ
T
0.5T
0.5T
3
Max
200
0.6T
0.6T
6
Units
ns
ns
ns
ns
3
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