DS90C241_0608 Datasheet, PDF (18/21 Pages) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Functional Description (Continued)
reduces supply current to the µA range. The Serializer enters
powerdown when the TPWDNB pin is driven low. In power-
down, the PLL stops and the outputs go into TRI-STATE,
disabling load current and reducing supply. To exit Power-
down, TPWDNB must be driven high. When the Serializer
exits Powerdown, its PLL must lock to TCLK before it is
ready for the Initialization state. The system must then allow
time for Initialization before data transfer can begin. The
Deserializer enters powerdown mode when RPWDNB is
driven low. In powerdown mode, the PLL stops and the
outputs enter TRI-STATE. To bring the Deserializer block out
of the powerdown state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and
relock before data can be transferred. The Deserializer will
initialize and assert LOCK high until it is locked to the input
clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN or
TPWDNB pin is driven low. This will TRI-STATE both driver
output pins (DOUT+ and DOUT−). When DEN is driven high,
the serializer will return to the previous state as long as all
other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deseri-
alizer enters TRI-STATE. Consequently, the receiver output
pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE.
The LOCK output remains active, reflecting the state of the
PLL. The Deserializer input pins are high impedance during
receiver powerdown (RPWDNB low) and power-off (V_CC =
0V).
PRE-EMPHASIS
The DS90C241 features a Pre-Emphasis mode used to
compensate for long or lossy transmission media. Cable
drive is enhanced with a user selectable Pre-Emphasis fea-
ture that provides additional output current during transitions
to counteract cable loading effects. The transmission dis-
tance will be limited by the loss characteristics and quality of
the media. Pre-Emphasis adds extra current during LVDS
logic transition to reduce the cable loading effects and in-
crease driving distance. In addition, Pre-Emphasis helps
provide faster transitions, increased eye openings, and im-
proved signal integrity. To enable the Pre-Emphasis function,
the “PRE” pin requires one external resistor (Rpre) to Vss in
order to set the additional current level. Pre-Emphasis
strength is set via an external resistor (Rpre) applied from
min to max (floating to 3kΩ) at the “PRE” pin. A lower input
resistor value on the ”PRE” pin increases the magnitude of
dynamic current during data transition. There is an internal
current source based on the following formula: PRE = (Rpre
≥ 3kΩ); I_MAX = [(1.2/Rpre) X 20]. The ability of the
DS90C241 to use the Pre-Emphasis feature will extend the
transmission distance up to 10 meters in most cases.
AC-COUPLING AND TERMINATION
The DS90C241 and DS90C124 supports AC-coupled inter-
connects through integrated DC balanced encoding/
decoding scheme. To use AC coupled connection between
the Serializer and Deserializer, insert external AC coupling
capacitors in series in the LVDS signal path as illustrated in
Figure 17. The Deserializer input stage is designed for AC-
coupling by providing a built-in AC bias network which sets
the internal V_CM to +1.2V. With AC signal coupling, capaci-
tors provide the ac-coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest avail-
able package should be used for the AC coupling capacitor.
This will help minimize degradation of signal quality due to
package parasitics. The most common used capacitor value
for the interface is 100 nF (0.1 uF) capacitor.
A termination resistor across DOUT± and RIN± is also
required for proper operation to be obtained. The termination
resistor should be equal to the differential impedance of the
media being driven. This should be in the range of 90 to 132
Ohms. 100 Ohms is a typical value common used with
standard 100 Ohm transmission media. This resistor is re-
quired for control of reflections and also to complete the
current loop. It should be placed as close to the Serializer
DOUT± outputs and Deserializer RIN± inputs to minimize
the stub length from the pins. To match with the deferential
impedance on the transmission line, the LVDS I/O are termi-
nated with 100 ohm resistors on Serializer DOUT± outputs
pins and Deserializer RIN± input pins.
PROGRESSIVE TURN–ON (PTO)
Deserializer ROUT[23:0] outputs are grouped into three
groups of eight, with each group switching about 0.5UI apart
in phase to reduce EMI, simultaneous switching noise, and
system ground bounce.
Applications Information
USING THE DS90C241 AND DS90C124
The DS90C241/DS90C124 Serializer/Deserializer (SER-
DES) pair sends 24 bits of parallel LVCMOS data over a
serial LVDS link up to 840 Mbps. Serialization of the input
data is accomplished using an on-board PLL at the Serializer
which embeds clock with the data. The Deserializer extracts
the clock/control information from the incoming data stream
and deserializes the data. The Deserializer monitors the
incoming clockl information to determine lock status and will
indicate lock by asserting the LOCK output high.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the LVDS outputs minimize the
slope of the speed vs. I_CC curve of CMOS designs.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic
factors include:
Serializer: TCLK jitter, V_CC noise (noise bandwidth and
out-of-band noise)
Media: ISI, V_CM noise
Deserializer: V_CC noise
For a graphical representation of noise margin, please see
Figure 15.
TRANSMISSION MEDIA
The Serializer and Deserializer can be used in point-to-point
configuration, through a PCB trace, or through twisted pair
cable. In a point-to-point configuration, the transmission me-
dia needs be terminated at both ends of the transmitter and
receiver pair. Interconnect for LVDS typically has a differen-
tial impedance of 100 Ohms. Use cables and connectors
that have matched differential impedance to minimize im-
pedance discontinuities. In most applications that involve
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