DS90C241_0608 Datasheet, PDF (1/21 Pages) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

October 2006
DS90C241/DS90C124
5-35MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS90C241/124 Chipset translates a 24-bit parallel bus
into a fully transparent data/control LVDS serial stream with
embedded clock information. This single serial stream sim-
plifies transferring a 24-bit bus over PCB traces and cable by
eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths
that in turn reduce PCB layers, cable width, and connector
size and pins.
The DS90C241/124 incorporates LVDS signaling on the
high-speed I/O. LVDS provides a low power and low noise
environment for reliably transferring data over a serial trans-
mission path. By optimizing the serializer output edge rate
for the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects.
Features
n 5 MHz–35 MHz clock embedded and DC-Balancing
24:1 and 1:24 data transmissions
n User defined Pre-Emphasis driving ability through
external resistor on LVDS outputs and capable to drive
up to 10 meters shielded twisted-pair cable
n User selectable clock edge for parallel data on both
Transmitter and Receiver
n Internal DC Balancing encode/decode – Supports
AC-coupling interface with no external coding required
n Individual power-down controls for both Transmitter and
Receiver
n Embedded clock CDR (clock and data recovery) on
Receiver and no external source of reference clock
needed
n All codes RDL (random data lock) to support
hot-pluggable applications
n LOCK output flag to ensure data integrity at Receiver
side
n Balanced T_SETUP/T_HOLD between RCLK and RDATA on
Receiver side
n PTO (progressive turn-on) LVCMOS outputs to reduce
EMI and minimize SSO effects
n All LVCMOS inputs and control pins have internal
pulldown
n On-chip filters for PLLs on Transmitter and Receiver
n 48-pin TQFP package
n Pure CMOS .35 µm process
n Power supply range 3.3V ± 10%
n Temperature range –40˚C to +105˚C
n 8 kV HBM ESD structure
Block Diagram
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