DS90C241_0608 Datasheet, PDF (19/21 Pages) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Applications Information (Continued)
cables, the transmission distance will be determined on data
rates involved, acceptable bit error rate and transmission
medium.
HOT PLUG INSERTION
The Serializer and Deserializer devices support hot plug-
gable applications. The “Hot Inserted” operation on the serial
interface does not disrupt communication data on the active
data lines. The automatic receiver lock to random data “plug
& go” hot insertion capability allows the DS90C124 to attain
lock to the active data stream during a live insertion event.
PCB LAYOUT AND POWER SYSTEM
CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SERDES
devices should be designed to provide low-noise power feed
to the device. Good layout practice will also separate high
frequency or high-level inputs and outputs to minimize un-
wanted stray noise pickup, feedback and interference.
Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sand-
wiches. This arrangement provides plane capacitance for
the PCB power system with low-inductance parasitics, which
has proven especially effective at high frequencies, and
makes the value and placement of external bypass capaci-
tors less critical. External bypass capacitors should include
both RF ceramic and tantalum electrolytic types. RF capaci-
tors may use values in the range of 0.01 uF to 0.1 uF.
Tantalum capacitors may be in the 2.2 uF to 10 uF range.
Voltage rating of the tantalum capacitors should be at least
5X the power supply voltage being used.
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per sup-
ply pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low
frequency switching noise. It is recommended to connect
power and ground pins directly to the power and ground
planes with bypass capacitors connected to the plane with
via on both ends of the capacitor. Connecting power or
ground pins to an external bypass capacitor will increase the
inductance of the path.
A small body size X7R chip capacitor, such as 0603, is
recommended for external bypass. Its small body size re-
duces the parasitic inductance of the capacitor. The user
must pay attention to the resonance frequency of these
external bypass capacitors, usually in the range of 20-30
MHz range. To provide effective bypassing, multiple capaci-
tors are often used to achieve low impedance between the
supply rails over the frequency of interest. At high frequency,
it is also a common practice to use two vias from power and
ground pins to the planes, reducing the impedance at high
frequency.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some
cases, an external filter many be used to provide clean
power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground
plane. Locate LVCMOS (LVTTL) signals away from the
LVDS lines to prevent coupling from the CMOS lines to the
LVDS lines. Closely-coupled differential lines of 100 Ohms
are typically recommended for LVDS interconnect. The
closely coupled lines help to ensure that coupled noise will
appear as common-mode and thus is rejected by the receiv-
ers. The tightly coupled lines will also radiate less.
Termination of the LVDS interconnect is required. For point-
to-point applications, termination should be located at both
ends of the devices. Nominal value is 100 Ohms to match
the line’s differential impedance. Place the resistor as close
to the transmitter DOUT± outputs and receiver RIN± inputs
as possible to minimize the resulting stub between the ter-
mination resistor and device.
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
— S = space between the pair
— 2S = space between pairs
— 3S = space to LVCMOS/LVTTL signal
• Minimize the number of VIA
• Use differential connectors when operating above
500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as
possible
Additional general guidance can be found in the LVDS Own-
er’s Manual - available in PDF format from the National web
site at: www.national.com/lvds
19
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