DS92LV3241 Datasheet, PDF (24/30 Pages) National Semiconductor (TI) – 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer

FIGURE 19. BIST Diagram for Different Bit Error Cases
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TYPICAL APPLICATION CONNECTION
Figure 20 shows a typical application of the DS92LV3241 Se-
rializer (SER). The differential outputs utilize 100nF coupling
capacitors to the serial lines. Bypass capacitors are placed
near the power supply pins. A system GPO (General Purpose
Output) controls the PDB and BISTEN pins. In this application
the R_FB (SER) pin is tied Low to latch data on the falling
edge of the TxCLKIN. In this application the link is short,
therefore the VSEL pin is tied LOW for the standard output
swing level. The Pre-emphasis input utilizes a resistor to
ground to set the amount of pre-emphasis desired by the ap-
plication.
Configuration pins for the typical application are shown for
SER:
• PDB – Power Down Control Input – Connect to host or tie
HIGH (always ON)
• BISTEN – Mode Input - tie LOW if BIST mode is not used,
or connect to host
• VSEL – tie LOW for normal VOD magnitude (application
dependant)
• MODE – For clock rates between 20 MHz and 50 MHz tie
LOW, for 40 MHz to 85 MHz tie HIGH
• PRE – Leave open if not required (have a R pad option on
PCB)
• RSVD1 & RSVD2 – tie LOW
There are eight power pins for the device. These may be
bussed together on a common 3.3V plane (3.3V LVCMOS I/
O interface). If 1.8V input swing level for parallel data and
control pins are required, connect the IOVDD pin to 1.8V. At
a minimum, eight 0.1uF capacitors should be used for local
bypassing.
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