DS92LV3241 Datasheet, PDF (12/30 Pages) National Semiconductor (TI) – 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer

Symbol
Parameter
Conditions
Min
Typ
DESERIALIZER LVDS DC SPECIFICATIONS
V_TH
Differential Threshold High Voltage V_CM = +1.8V
V_TL
Differential Threshold Low Voltage
−50
R_T
Input Termination
Internal differential output termination
90
100
between differential pairs
I_IN
Input Current
V_IN = +2.4V, V_DD = 3.6V
±100
V_IN = 0V, V_DD = 3.6V
±100
DESERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
I_DDR
Deserializer Total Supply Current
f = 85 MHz,
(includes load current)
C_L = 8 pF,
240
CHECKER BOARD pattern,
Quad Mode
f = 85 MHz,
C_L = 8 pF,
190
RANDOM pattern,
Quad Mode
f = 50 MHz,
C_L = 8 pF,
145
CHECKER BOARD pattern,
Dual Mode
f = 50 MHz,
C_L = 8 pF,
122
RANDOM pattern,
Dual Mode
I_DDRZ
Deserializer Supply Current Power-
down
PDB = 0V
(All other LVCMOS Inputs = 0V,
RxIN[3:0](P/N) = 0V)
Max
+50
130
±250
±250
265
210
185
140
100
Units
mV
mV
Ω
µA
µA
mA
mA
µA
Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t_CIP
TxCLKIN Period
MODE = L (Dual Mode)
MODE = H (Quad Mode)
t_CIH
TxCLKIN High Time
20 MHz – 50 MHz
40 MHz – 85 MHz
t_TCIL
TxCLKIN Low Time
20 MHz – 50 MHz
Figure 7
40 MHz – 85 MHz
t_CIT
TxCLKIN Transition Time
20 MHz – 50 MHz
Figure 6
40 MHz – 85 MHz
t_JIT
TxCLKIN Jitter
Min
Typ
Max
20
t_CIP
50
11.76
t_CIP
25
0.45 x
t_CIP
0.45 x
t_CIP
0.45 x
t_CIP
0.45 x
t_CIP
0.5 x t_CIP
0.5 x t_CIP
0.5 x t_CIP
0.5 x t_CIP
0.55 x
t_CIP
0.55 x
t_CIP
0.55 x
t_CIP
0.55 x
t_CIP
0.5
1.2
0.5
1.2
±100
Units
ns
ns
ns
ns
ps_P-P
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