DS92LV3241 Datasheet, PDF (23/30 Pages) National Semiconductor (TI) – 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer

[31:0]) are ignored and the DES outputs (RxOUT[31:0]) are
not available. Next, the internal test pattern generator for each
channel starts transmission of the BIST pattern from SER to
DES. The DES BIST mode will be automatically activated by
this sequence. A maximum of 128 consecutives clock sym-
bols on DS92LV3242 DES is needed to detect BIST enable
function. The BIST is implemented with independent transmit
and receive paths for the four serial links. Each channel on
the DES will be individually compared against the expected
bit sequence of the BIST pattern.
FIGURE 18. BIST Test Enabled/Disabled
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Under the BIST mode, the DES parallel outputs on RxOUT
[31:0] are multiplexed to represent BIST status indicators.
The pass/fail status of the BIST is represented by a Pass flag
along with an Error counter. The Pass flag output is desig-
nated on DES RxOUT0 for Channel 0, and RxOUT8 for
Channel 1. The DES's PLL must first be locked to ensure the
Pass status is valid. The output Pass status pin will stay LOW
and then transition to High once 44*10^6 symbols are
achieved across each of the respective transmission links.
The total time duration of the test is defined by the following:
44*10^6 x tCIP . After the Pass output flags reach a HIGH
state, it will not drop to LOW even if subsequent bit errors
occurred after the BIST duration period. Errors will be report-
ed if the input test pattern comparison does not match. If an
error (miss-compare) occurs, the status bit is latched on Rx-
OUT[7:1] for Channel 0, and RxOUT[15:9] for Channel 1;
reflecting the number of errors detected. Whenever a data bit
contains an error, the Error counter bit output for that corre-
sponding channel goes HIGH. Each counter for the serial link
utilizes a 7-bit counter to store the number of errors detected
(0 to 127 max).
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