DS92LV3241 Datasheet, PDF (13/30 Pages) National Semiconductor (TI) – 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer

Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Units
t_LLHT
t_LHLT
t_STC
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
TxIN[31:0] Setup to TxCLKIN
No pre-emphasis
Figure 5
IOVDD = 1.71V to 1.89V
Figure 7
IOVDD = 3.135V to 3.465V
350
ps
350
ps
0
ns
0
t_HTC
TxIN[31:0] Hold from TxCLKIN
IOVDD = 1.71V to 1.89V
2.5
ns
IOVDD = 3.135V to 3.465V
2.25
t_PLD
Serializer PLL Lock Time
Figure 9
t_LZD
Data Output LOW to TRI-STATE® (Note 4)
Delay
t_HZD
Data Output TRI-STATE® to HIGH (Note 4)
Delay
t_SD
Serializer Propagation Delay -
f = 50 MHz,
Latency
R_FB = H,
PRE = OFF,
MODE = L
Figure 8
f = 50 MHz,
R_FB = L,
PRE = OFF,
MODE = L
4400 x 5000 x
t_CIP
t_CIP
ns
5
10
ns
5
10
ns
4.5 t_CIP +
6.77
4.5 t_CIP + 4.5 t_CIP + 4.5 t_CIP +
5.63
7.09
9.29
f = 20 MHz,
R_FB = H,
PRE = OFF,
MODE = L
f = 85MHz,
R_FB = H,
PRE = OFF,
MODE = H
4.5 t_CIP + 4.5 t_CIP + 4.5 t_CIP +
6.57
8.74 10.74
ns
9.0 t_CIP +
6.99
f = 85MHz,
R_FB = L,
PRE = OFF,
MODE = H
9.0 t_CIP + 9.0 t_CIP + 9.0 t_CIP +
5.97
7.38
9.64
f = 40 MHz,
R_FB = HL,
PRE = OFF,
MODE = H
9.0 t_CIP + 9.0 t_CIP + 9.0 t_CIP +
6.30
8.26 10.49
t_LVSKD
LVDS Output Skew
LVDS differential output channel-to-
channel skew
30
500
ps
13
www.national.com