DS92LV3241 Datasheet, PDF (15/30 Pages) National Semiconductor (TI) – 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer

Symbol
t_RD
Parameter
Deserializer Porpagation Delay –
Latency
Conditions
f = 20 MHz
(Dual Mode)
Figure 12
f = 50 MHz
(Dual Mode)
f = 40 MHz
(Quad Mode)
f = 85 MHz
(Quad Mode)
t_RPLLS
TOL_JIT
t_LVSKR
Deserializer PLL Lock Time
Deserializer Input Jitter Tolerance
LVDS Differential Input Skew
Tolerance
20 MHz – 50 MHz
(Dual Mode)
Figure 13
(Note 5)
40 MHz – 85 MHz
(Quad Mode)
Figure 13
(Note 5)
20 MHz – 85 MHz
Figure 17
Min
Typ
Max Units
5.5 x
ns
t_ROCP +
3.35
5.5 x
ns
t_ROCP +
6.00
12.0 x
ns
t_ROCP +
7.4
12.0 x
ns
t_ROCP +
5.7
128k x
t_ROCP
ns
256k x
t_ROCP
ns
0.25
UI
0.4 x
t_ROCP
ns
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: Typical values represent most likely parametric norms at V_DD = 3.3V, T_A = +25°C, and at the Recommended Operating Conditions at the time of product
characterization and are not guaranteed.
Note 3: Current into a the device is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except V_OD,
ΔV_OD, V_TH, V_TL which are differential voltages.
Note 4: When the Serializer output is at TRI-STATE® the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 5: t_RPLLS is the time required by the Deserializer to obtain lock when exiting power-down mode.
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