DS92LV3241 Datasheet, PDF (21/30 Pages) National Semiconductor (TI) – 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer

Functional Description
The DS92LV3241 Serializer (SER) and DS92LV3242 Dese-
rializer (DES) chipset is a flexible SER/DES chipset that
translates a 32-bit parallel LVCMOS data bus into a quad (4
pairs) or dual (2 pairs) LVDS serial links with embedded clock.
The DS92LV3241 serializes the 32-bit wide parallel LVCMOS
word into four or two high-speed LVDS serial data streams
with embedded clock, scrambles and DC Balances the data
to support AC coupling and enhance signal quality. The
DS92LV3242 receives the dual/quad LVDS serial data
streams and converts it back into a 32-bit wide parallel data
with a recovered clock. The dual/quad LVDS serial data
stream reduces cable size, the number of connectors, and
eases skew concerns.
Parallel clocks between 20 MHz to 85 MHz are supported by
the dual or quad operating modes. The modes are user se-
lectable through a control pin on Serializer. In dual mode, the
transmit clock frequency supports 20 MHz to 50 MHz and in
quad mode the transmit clock frequency supports 40 MHz to
85 MHz. In the dual mode configuration, the embedded clock
LVDS serial streams have an effective data payload of 640
Mbps (20MHz x 32-bit) to 1.6 Gbps (50MHz x 32- bit). In the
quad mode configuration, the embedded clock LVDS serial
streams have an effective data payload of 1.28 Gbps (40MHz
x 32-bit) to 2.72 Gbps (85MHz x 32-bit). The SER/DES
chipset is designed to transmit data over long distances
through standard twisted pair (TWP) cables. The differential
inputs and outputs are internally terminated with 100 ohm re-
sistors to provide source and load termination, minimize stub
length, to reduce component count and further minimize
board space.
The DES can attain lock to a data stream without the use of
a separate reference clock source; greatly simplifying system
complexity and reducing overall cost. The DES synchronizes
to the SER regardless of data pattern, delivering true auto-
matic “plug-and-lock” performance. It will lock to the incoming
serial stream without the need of special training patterns or
special sync characters. The DES recovers the clock and data
by extracting the embedded clock information, deskews the
serial data channels and then deserializes the data. The DES
also monitors the incoming clock information, determines lock
status, and asserts the LOCK output high when lock occurs.
In addition the DES also supports an optional AT-SPEED
BIST (Built In Self Test) mode, BIST error flag, and LOCK
status reporting pin. The SER and the DES have a power
down control signal to enable efficient operation in various
applications.
DESKEW AND CHANNEL ALIGNMENT
The DES automatically detects dual or quad serial channel
mode and provides a clock alignment and deskew function
without the need for any special training patterns. During the
locking phase, the embedded clock information is recovered
on all channels and the serial links are internally synchro-
nized, de-skewed, and auto aligned. The internal CDR cir-
cuitry will dynamically compensate for up to 0.4 times the
parallel clock period of per channel phase skew (channel-to-
channel) between the recovered clocks of the serial links. This
provides skew phase tolerance from mismatches in intercon-
nect wires such as PCB trace routing, cable pair-to-pair length
differences, and connector imbalances.
DATA TRANSFER
After SER lock is established (SER PLL to TxCLKIN), the in-
puts TxIN0–TxIN31 are latched into the encoder block. Data
is clocked into the SER by the TxCLKIN input. The edge of
TxCLKIN used to strobe the data is selectable via the R_FB
(SER) pin. R_FB (SER) high selects the rising edge for clock-
ing data and low selects the falling edge. The SER outputs
(TxOUT[3:0]+/-) are intended to drive a AC Coupled point-to-
point connections.
The SER latches 32-bit parallel data bus and performs sev-
eral operations to it. The 32-bit parallel data is internally
encoded and sequentially transmitted over the two high-
speed serial LVDS channels. For each serial channel, the
SER transmits 20 bits of information per payload to the DES.
In the dual mode, the 32-bit parallel data is scaled and bit-
mapped across two 20-bit data payloads per channel, result-
ing in a per channel throughput of 400 Mbps to 1.0 Gbps (20
bits x clock rate). Under quad mode, the internal PLL operates
at ½ the input clock frequency rate. The 32 bits are bit-
mapped and sequenced per every 2 cycles at ½ the TxCLKIN
frequency across four channels, resutling in a per channel
throughput of 400 Mbps to 850 Mbps (20 bits x clock rate/2).
The chipset supports frequency ranges of 20 MHz to 85 MHz.
When all of the DES channels obtain lock , the LOCK pin is
driven high and synchronously delivers valid data and recov-
ered clock on the output. The DES locks to the clock, uses it
to generate multiple internal data strobes, and then drives the
recovered clock to the RxCLKOUT pin. The recovered clock
(RxCLKOUT) is synchronous to the data on the RxOUT[31:0]
pins. While LOCK is high, data on RxOUT[31:0] is valid. Oth-
erwise, RxOUT[31:0] is invalid. The polarity of the RxCLK-
OUT edge is controlled by its R_FB (DES) input. RxOUT
[31:0], LOCK and RxCLKOUT outputs will each drive a max-
imum of 8 pF load. REN controls TRI-STATE® for RxOUT0–
RxOUT31 and the RxCLKOUT pin on the DES.
RESYNCHRONIZATION
In the absence of data transitions on one of the channels into
the DES (e.g. a loss of the link), it will automatically try to
resynchronize and re-establish lock using the standard lock
sequence on the master channel (Channel 0). For example,
if the embedded clock is not detected one time in succession
on any of the serial links, the LOCK pin is driven low. The DES
then monitors the master channel for lock, once that is ob-
tained, the second channel is locked and aligned. The logic
state of the LOCK signal indicates whether the data on Rx-
OUT is valid; when it is high, the data is valid. The system
may monitor the LOCK pin to determine whether data on the
RxOUT is valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the SER
and DES may use to reduce power when no data is being
transferred. The respective PDB pins are used to set each
device into power down mode, which reduces supply current
into the µA range. The SER enters Powerdown when the SER
PDB pin is driven low. In Powerdown, the PLL stops and the
outputs go into TRI-STATE®, disabling load current and re-
ducing current supply. To exit Powerdown, SER PDB must
be driven high. When the SER exits Powerdown, its PLL must
lock to TxCLKIN before it is ready for sending data to the DES.
The system must then allow time for the DES to lock before
data can be recovered.
The DES enters Powerdown mode when DES PDB is driven
low. In Powerdown mode, the PLL’s stop and the outputs en-
ter TRI-STATE®. To bring the DES block out of the Power-
down state, the system drives DES PDB high. Both the SER
and DES must relock before data can be transferred from
Host and received by the Target. The DES will startup and
assert LOCK high when it is locked to the embedded clocks.
See also Figure 13.
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