COP87L88RW Datasheet, PDF (18/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller with Pulse Train Generators and Capture Modules

Multiply Divide (Continued)
CONTROL REGISTER BITS
The Multiply Divide control register (MDCR) is located at
address xx9D It has the following bit assignments
MULT Start Multiplication Operation (1 e start)
DIV Start Division Operation (1 e start)
DIVOVF Division Overflow (if the result of a division is
greater than 16 bits or the user attempted to divide
by zero 1 e error)
Rsvd Rsvd Rsvd Rsvd Rsvd DIV DIV MULT
OVF
Bit 7
Bit 0
After the appropriate MDR registers are loaded the MULT
and DIV start bits are set by the user to start a multiply or
divide operation The division operation has priority if both
bits are set simultaneously The MULT and DIV bits are
BOTH automatically cleared by hardware at the end of a
divide or multiply operation Each division operation causes
the DIVOVF flag to be set reset as appropriate The
DIVOVF flag is cleared following a multiplication operation
DIVOVF is a read-only bit The MULT and DIV bits are read
writable Bits 3 – 7 in MDCR should not be used as the
MULT and DIV operations will change their values
MULTIPLY DIVIDE OPERATION
For the multiply operation the muItiplicand is placed at ad-
dresses xx9B and xx9C The multiplier is placed at address
xx99 For the divide operation the dividend is placed at ad-
dresses xx98 to xx9A and the divisor is placed at addresses
xx9B to xx9C In both operations all operands are interpret-
ed as unsigned values The divide or multiply operation is
started by setting the appropriate MDCR bit If both the
MULT and DIV bits are set the microcontroller performs a
divide operation (The user is not required to read or clear
the DIVOVF error bit prior to beginning a new multiply di-
vide operation This bit is ignored during subsequent opera-
tions However the next divide operation will overwrite the
error flag as appropriate and the next multiply operation will
clear it )
The multiply operation requires 1 instruction cycle to com-
plete The divide operation requires 2 instruction cycles to
complete A divide by zero or a division which produces an
overflow requires only 1 instruction cycle to execute The
MDR1 through MDR5 registers and the MDCR register can
not be read from or written to during a multiply or divide
operation Any attempt to write into these registers will be
ignored Any attempt to read these registers will return un-
defined data
The result of a multiply is placed in addresses xx99-xx9B
The result of a divide is placed in addresses xx98-xx99 If a
division by zero is attempted or if the resulting quotient of a
divide operation is more than 16 bits long then the DIVOVF
bit is set in the multiply divide control register The dividend
and the divisor are left unchanged The divide operation al-
ways causes the DIVOVF flag to be set or reset as appropri-
ate The DIVOVF flag is cleared following a multiply opera-
tion
RESET STATE
A reset signal applied to the device during normal operation
has the following affects
MDCR is cleared and any operation in progress is stopped
MDR1 through MDR5 are undefined
Power Save Modes
The device offers the user two power save modes of opera-
tion HALT and IDLE In the HALT mode all microcontroller
activities are stopped In the IDLE mode the on-board oscil-
lator circuitry and timer T0 are active but all other microcon-
troller activities are stopped In either mode all on-board
RAM registers I O states and timers (with the exception of
T0) are unaltered
HALT MODE
The device can be placed in the HALT mode by writing a
‘‘1’’ to the HALT flag (G7 data bit) All microcontroller activi-
ties including the clock and timers are stopped In the
HALT mode the power requirements of the device are mini-
mal and the applied voltage (V_CC) may be decreased to V_r
(V_r e 2 0V) without altering the state of lhe machine
The device supports two different ways of exiting the HALT
mode The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the L port The second meth-
od of exiting the HALT mode is by pulling the RESET pin
low
Since a crystal or ceramic resonator may be selected as the
oscillator the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability The IDLE timer is used to gen-
erate a fixed deIay to ensure that the oscilIator has indeed
stabilized before allowing instruction execution In this case
upon detecting a valid Wakeup signal only the oscillator
circuitry is enabled The IDLE timer is loaded with a value of
256 and is clocked with the t_c instruction cycle clock The t_c
clock is derived by dividing the oscillator clock down by a
factor of 10 The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications This Schmitt trigger
is not part of the oscillator closed loop The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip
The devices have two mask options associated with the
HALT mode The first mask option enables the HALT mode
feature while the second mask option disables the HALT
mode With the HALT mode enable mask option the device
will enter and exit the HALT mode as described above With
the HALT disable mask option the device cannot be placed
in the HALT mode (writing a ‘‘1’’ to the HALT flag will have
no effect the HALT flag will remain ‘‘0’’)
IDLE MODE
The device is placed in the IDLE mode by writing a ‘‘1’’ to
the IDLE flag (G6 data bit) In this mode all activities except
the associated on-board oscillator circuitry and the IDLE
Timer T0 are stopped
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