COP87L88RW Datasheet, PDF (14/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller with Pulse Train Generators and Capture Modules

Timers (Continued)
The CCMR2 Register Bits are
CM2RUN CM2 start stop control bit (1 start 0estop)
CM2IEN CM2 interrupt enable control bit (1e enable IRQ)
CM2IP1 CM2 interrupt pending bit 1 (1eCM2 under-
flowed)
CM2IP2 CM2 interrupt pending bit 2 (1eCM2 captured)
CM2EC Select the active edge for capture on CM2 (0 e
rising 1 e falling)
CM2TM CM2 test mode control bit (1 e speciaI test path
in test mode This bit is reserved during normal
operation and must never be set to one )
CM2 un- un- CM2 CM2 CM2 CM2 CM2
TM used used EC IP2 IP1 IEN RUN
Bit 7
Bit 0
AII interrupt pending bits must be reset by software
FUNCTIONAL DESCRIPTION
The capture timer is used to determine the time between
events where an event is simply a selected edge transition
on the capture input The resolution of the time measure-
ment is dependent on the frequency at which the down
counter is clocked The vaIue Ioaded into the prescaler con-
trols this frequency
The prescaIer is clocked by CKI while the down counter is
clocked on every underfIow of the prescaler This means
the prescaIer simpIy divides the CKI cIock before it is fed
into the down counter The prescaler register must be Ioad-
ed with a vaIue corresponding to the CKI divisor needed to
produce the desired down counter clock The appropriate
prescaler vaIue can be determined using the following
equation
Down Counter Clock Frequency e CKI (CMxPSC a 1)
The capture input signaI is set up by configuring the port pin
associated with the capture timer as an input The edge
seIect bit for the capture input is then set or reset according
to the desired transition If the pin is configured as an input
the appropriate externaI transition will cause a capture If
the pin is configured as an output toggling the data register
bit wiIl cause a capture If interrupts are used the capture
timer interrupt pending bits are cIeared and the capture tim-
er interrupt enable bit is set Both interrupt sources down
counter underflow and input capture edge are enabled dis-
abled with the same CMxIEN bit The GIE bit must also be
set to enable interrupts The interrupt signals from the two
capture timers are gated to a single 16-bit interrupt vector
located at addresses 0xE6 and 0xE7
The capture timer is started by writing a ‘‘1’’ to the capture
timer start stop bit Setting this bit also enables the port pin
to be the capture input to the capture timer The internal
prescaler is loaded with the contents of the prescaler regis-
ter and begins counting down Setting the start stop bit
also loads the down counter with 0FFFF Hex The prescaler
is clocked by CKI An underflow of the prescaler decre-
ments the 16-bit down counter and reloads the value from
the prescaler register into the prescaler Each additional un-
derflow of the prescaler decrements the down counter and
reloads the prescaler from the prescaler register
If a selected edge transition on the input capture pin occurs
the contents of the down counter are immediately latched
into the capture register the down counter is re-initialized to
0FFFF Hex and the capture input pending flag is set The
prescaler counter is not loaded (In order for an input tran-
sition to be guaranteed recognized the signal on the cap-
ture input pin must have a low pulse width and a high pulse
width of at least one CKI period ) If interrupts are enabled
the capture timer generates an interrupt The prescaler and
down counter continue to operate until a reset condition
occurs or the capture timer start stop bit is reset The user
must process capture interrupts faster than the capture in-
put frequency otherwise input captures may be lost or erro-
neous values may be read
If the down counter underflows (changes state from 0000 to
FFFF) before a capture input is detected the underflow in-
terrupt pending flag is set If interrupts are enabled the cap-
ture timer generates an interrupt
The capture timer may be stopped at any time under soft-
ware control by resetting the capture timer start stop bit A
capture may occur before the start stop bit is physically
cIeared due to the fully asynchronous nature of the input
capture signal The user must ensure that the software han-
dles this situation correctly If the user wishes to process
this capture and interrupts are being used the capture timer
interrupts should not be disabIed prior to stopping the timer
If interrupts are not being used the user should poll the
capture timer pending bits after stopping the timer If the
user wishes to ignore this capture and interrupts are being
used the capture timer interrupt service routine should
check that the timer is still running prior to processing cap-
ture interrupts If the user is polling the pending flags these
flags should be cleared after the timer is stopped The con-
tents of the prescaler and down counter remain unchanged
while the capture timer is stopped The capture edge detect
logic is disabled and no capture takes place even if an
external capture signal occurs The capture timer may be
restarted under software control by writing a ‘‘1’’ to the
start stop bit This causes the prescaler and down counter
to be re-initialized The prescaler is loaded from the prescal-
er register and the down counter is loaded with 0FFFF Hex
RESET STATE
A reset signal applied to the counter block during normal
operation has the following effects
 Clear CCMR1 register
 Clear CCMR2 register
 CM1PSC CMICRL CM1CRH CM2PSC CM2CRL and
CM2CRH are unaffected (At power-on the contents of
these registers are undefined )
The bi-directional port pins are initialized during reset as
HI-Z inputs Setting the start stop bits connects the pins to
the capture timers
http www national com
14