COP87L88RW Datasheet, PDF(11/42 Page) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller with Pulse Train Generators and Capture Modules

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COP87L88RW Datasheet, PDF (11/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller with Pulse Train Generators and Capture Modules

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Timers (Continued)

FIGURE 9 Timer in External Event Counter Mode

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In this mode the input pin TxB can be used as an indepen-

dent positive edge sensitive interrupt input if the TxENB

control flag is set The occurrence of a positive edge on the

TxB input pin is latched into the TxPNDB flag

Figure 9 shows a block diagram of the timer in External

Event Counter mode

Note The PWM output is not available in this mode since the TxA pin is

being used as the counter input clock

Mode 3 Input Capture Mode

The device can precisely measure external frequencies or

time external events by placing the timer block Tx in the

input capture mode

In this mode the timer Tx is constantly running at the fixed

tc rate The two registers RxA and RxB act as capture

registers Each register acts in conjunction with a pin The

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin Control bits

TxC3 TxC2 and TxC1 allow the trigger events to be speci-

fied either as a positive or a negative edge The trigger con-

dition for each input pin can be specified independently

The trigger conditions can also be programmed to generate

interrupts The occurrence of the specified trigger condition

on the TxA and TxB pins will be respectively Iatched into the

pending flags TxPNDA and TxPNDB

The control flag TxENA allows the interrupt on TxA to be

either enabled or disabled Setting the TxENA flag enables

interrupts to be generated when the selected trigger condi-

tion occurs on the TxA pin Similarly the flag TxENB con-

trols the interrupts from the TxB pin

Underflows from the timer can also be programmed to gen-

erate interrupts Underflows are latched into the timer TxC0

pending flag (the TxC0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode) Con-

sequently the TxC0 control bit should be reset when enter-

ing the Input Capture mode The timer underflow interrupt is

enabled with the TxENA control flag When a TxA interrupt

occurs in the Input Capture mode the user must check both

the TxPNDA and TxC0 pending flags in order to determine

whether a TxA input capture or a timer underflow (or both)

caused the interrupt

Figure 10 shows a block diagram of the timer in Input Cap-

ture mode

FIGURE 10 Timer in Input Capture Mode

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