COP87L88RW Datasheet, PDF (13/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller with Pulse Train Generators and Capture Modules

Timers (Continued)
FIGURE 11 Capture Timer 1 Block Diagram
TL DD 12855 – 11
The registers shown in the block diagram include those for
Capture Timer 1 (CM1) as well as the capture timer 1 con-
trol register These registers are read writable (with the ex-
ception of the capture registers which are read-only) and
may be accessed through the data memory address data
bus The registers are designated as
CM1PSC Capture Timer 1 Prescaler (8-bit)
CM1CRL Capture Timer 1 Capture Register (Low-byte)
read-only
CM1CRH Capture Timer 1 Capture Register (High-byte)
read-only
CM2PSC Capture Timer 2 Prescaler (8-bit)
CM2CRL Capture Timer 2 Capture Register (Low-byte)
read-only
CM2CRH Capture Timer 2 Capture Register (High-byte)
read-only
CCMR1 Control Register for Capture Timer 1
CCMR2 Control Register for Capture Timer 2
CONTROL REGISTER BITS
The control bits for Capture Timer 1 (CM1) and Capture
Timer 2 (CM2) are contained in CCMR1 and CCMR2
The CCMR1 Register Bits are
CM1RUN CM1 start stop control bit (1 e start 0 e stop)
CM1IEN CM1 interrupt enable control bit (1 e enable
IRQ)
CM1IP1 CM1 interrupt pending bit 1 (1 e CM1 under-
flowed)
CM1IP2 CM1 interrupt pending bit 2 (1 e CM1 captured)
CM1EC Select the active edge for capture on CM1 (0 e
rising 1 e falling)
CM1TM
CM1 test mode control bit (1 e special test path
in test mode This bit is reserved during normal
operation and must never be set to one )
CM1 un- un- CM1 CM1 CM1 CM1 CM1
TM used used EC IP2 IP1 IEN RUN
Bit 7
Bit 0
All interrupt pending bits must be reset by software
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