COP87L88RW Datasheet, PDF (16/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller with Pulse Train Generators and Capture Modules

Pulse Train Generators (Continued)
The four 8-bit registers shown in each individual counter in
the block diagram constitute a 16-bit prescaler and a 16-bit
count register These registers are all read writable and
may be accessed through the data memory address data
bus The registers are designated as
CxPRL Low-byte of the Prescaler
CxPRH High-byte of the Prescaler
CxCTL Low-byte of the Count Register
CxCTH High-byte of the Count Register
CONTROL REGISTER BITS
The control bits for Counter 1 and Counter 2 are contained
in the CCR1 register The CCR1 Register bits are
C1RUN COUNTER1 start stop control bit (1 e start 0 e
stop)
C1IEN COUNTER1 interrupt enable control bit (1 e en-
able IRQ)
C1IPND COUNTER1 interrupt pending bit (1 e counter 1
underflowed)
C1TM
COUNTER1 test mode control bit (1especial test
path in test mode This bit is reserved during nor-
mal operation and must never be set to one )
C2RUN COUNTER2 start stop control bit (1 e start 0 e
stop)
C2IEN COUNTER2 interrupt enable control bit (1e en-
able IRQ)
C2IPND COUNTER2 interrupt pending bit (1 e counter 2
underflowed)
C2TM
COUNTER2 test mode control bit (1especial test
path This bit is reserved during normal operation
and must never be set to one )
All interrupt pending bits must be reset by software
C2TM C2 C2 C2 C1TM C1 C1 C1
IPND IEN RUN
IPND IEN RUN
Bit 7
Bit 0
The control bits for Counter 3 and Counter 4 are contained
in the CCR2 register The CCR2 Register bits are
C3RUN COUNTER3 start stop control bit (1 estart 0 e
stop)
C3IEN COUNTER3 interrupt enable control bit (1 e en-
able IRQ)
C3IPND COUNTER3 interrupt pending Bit (1ecounter 3
underflowed)
C3TM
COUNTER3 test mode control bit (1especial test
path This bit is reserved during normal operation
and must never be set to one )
C4RUN COUNTER4 start stop control bit (1 e start 0 e
stop)
C4IEN COUNTER4 interrupt enable control bit (1 e en-
able IRQ)
C4IPND COUNTER4 interrupt pending bit (1 ecounter 4
underflowed
C4TM
COUNTER4 test mode control bit (1 especial test
path This bit is reserved during normal operation
and must never be set to one )
C4TM C4 C4 C4 C3TM C3 C3 C3
IPND IEN RUN
IPND IEN RUN
Bit 7
Bit 0
All interrupt pending bits must be reset by software
FUNCTIONAL DESCRIPTION
The pulse train generator may be used to produce a series
of output pulses of a given width The high low time of a
pulse is determined by the contents of the prescaler The
number of pulses in a series is determined by the contents
of the count register
The prescaler is loaded with a value corresponding to the
desired width of the output pulse (t_w) The high time and low
time of the output signal are each equal to t_w therefore the
output signal produced has a 50% duty cycle and a period
equal to 2 t_w The appropriate prescaler value can be
determined using the following equation
t_w e (PRH 256) a PRL a 1 t_c
Since PRH and PRL are both 8-bit registers this equation
allows a maximum t_w of 65536 t_c and a minimum t_w of one
t_c The internal prescaler is automatically loaded from PRH
and PRL when the counter start stop bit is set
The count register is loaded with a value corresponding to
the desired number of output pulses The appropriate count
value is calculated with the following equation
Number of Pulses e CTH 256 a CTL a 1
The port pin associated with the counter OUT signal is con-
figured in software as an output and preset to the desired
start logic level lf interrupts are to be used the counter
interrupt pending bit is cleared and the interrupt enable bit is
set The GIE bit must also be set to enable interrupts The
interrupt signals from the four counters are gated to a single
interrupt vector located at addresses 0xF0 – 0xF1
The counter is started by writing a ‘‘1’’ to the counter start
stop bit This resets the divide-by-2 counter which produces
the clock signal for the counter register from the prescaler
underflow (See Figure 12 ) It also reloads the internal pre-
scaler and starts the prescaler counting down on the next
rising edge of t_c The prescaler is clocked on the rising edge
of t_c to ensure synchronization Each subsequent rising
edge of t_c causes the prescaler to be decremented When
the prescaler underflows UFL1 is generated (see Figure
13 ) This signal causes the port pin to toggle In addition the
internal prescaler is reloaded with the value from the PRH
and PRL registers Each additional underflow of the prescal-
er causes the port pin to toggle and reloads the internal
prescaler
Every second underflow of the prescaler generates the sig-
nal UFL2 (UFL2 occurs at half the frequency of UFL1 or
once per output pulse ) This signal UFL2 decrements the
count register Therefore the count registers are decre-
mented once per output pulse
http www national com
16