COP87L88RW Datasheet, PDF (17/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller with Pulse Train Generators and Capture Modules

Pulse Train Generators (Continued)
The underflow of the counter register produces the signal
UFL3 This signal stops the counter by resetting the counter
start stop bit and sets the counter interrupt pending flag If
the counter interrupt is enabled an interrupt occurs
The counter may be stopped at any time under software
control by resetting the counter start stop bit The contents
of the count register and the output on the associated port
pin are frozen The counter may be restarted under software
control by setting the start stop bit The internal prescaler is
automatically reloaded from PRH and PRL when the coun-
ter start stop bit is set therefore a full width pulse will be
generated before the output is toggled The user may also
choose to alter the logic level on the port pin before restart-
ing This is done by initializing the associated port pin data
register bit A counter underflow may occur before the start
stop bit is physically cleared by software The user must
ensure that the software handles this situation correctly If
the user wishes to process this underflow and interrupts are
being used the counter interrupts should not be disabled
prior to stopping the timer If interrupts are not being used
the user should poll the counter pending bits after stopping
the timer If the user wishes to ignore this underflow and
interrupts are being used the counter interrupt should be
disabled prior to stopping the timer If the user is polling the
pending flags these flags should be cleared after the timer
is stopped
If the default level of the output pin is high (associated port
data register bit is set to ‘‘1’’) and the counter is stopped
during a low level the low level becomes the default level
The software must reinitialize the port pin to a high level
before restarting if necessary The programmer may also
have to adjust the counter value
RESET STATE
A reset signal applied to the pulse train generator block
during normal operation has the following effects
 Counting stops immediately
 Interrupt enable bit is reset to zero
 Counter start stop bit is reset to zero
 Interrupt pending bit is reset to zero
 Test mode controI bit is reset to zero
 PRL PRH CTL and CTH are unaffected (At power-on
reset the contents of the prescaler and count register
are undefined )
 Divide-by-2 counter is reset
 The bi-directional port pins are initialized during reset as
HI-Z inputs The appropriate bits must be initialized as
outputs in order to route the Counter OUT signals to the
port pins
INITIALIZATION
The user should perform the following initialization prior to
starting the counter
1 Load PRL register
2 Load PRH register
3 Load CTL register
4 Load CTH register
5 Reset CxIPND bit
6 Set CxIEN (if interrupt is to be used)
7 Configure the associated port bit as an output (if OUT is
to be used)
8 Set the Global Interrupt Enable (GIE) bit (if interrupt is to
be used)
9 Set CxRUN bit to start counter
Multiply Divide
This device contains a multiply divide block This block sup-
ports a 1 byte x 2 bytes (3 bytes result) multiply or a 3 bytes
2 bytes (2 bytes result) divide operation The multiply or
divide operation is executed by setting control bits located
in the multiply divide control register The multiply or divide
operands must be placed into the appropriate memory
mapped locations before the operation is initiated
Register Name
(Address)
MDR1 (xx98)
MDR2 (xx99)
MDR3 (xx9A)
MDR4 (xx9B)
MDR5 (xx9C)
TABLE III Multiply Divide Registers
Multiplication Assignment
Before Operation
After Operation
Unused
Unchanged
Multiplier
Low byte of result
Middle byte of result
Low byte of multiplicand
High byte of result
High byte of multiplicand
Unchanged
Division Assignment
Before Operation
After Operation
Low byte of dividend
Low byte of result
Middle byte of dividend
High byte of result
High byte of dividend
Undefined
Low byte of divisor
Low byte of divisor
High byte of divisor
High byte of divisor
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