LP2975 Datasheet, PDF (17/19 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

Application Hints (Continued)
Low ESR Unstable without Feed-Forward
DS100034-30
This application can also be improved by adding a feed-
forward capacitor. C_F will add both a zero f_zf and pole f_pf to
the gain plot (see graph LOW ESR CORRECTED WITH
FEED-FORWARD).
The crossover frequency f_c is now about 10 kHz. If C_F is se-
lected so that f_zf is about 5 kHz, and f_pf is about 20 kHz
(which means V_OUT = 5V), the phase margin will be consid-
erably improved. Calculating out all the poles and zeroes,
the phase margin is increased from 9˚ to 43˚ (adequate for
good stability).
Low ESR Corrected with Feed-Forward
The use of a feed-forward capacitor C_F will help reduce ex-
cess phase shift due to f_pg, but its effectiveness depends on
output voltage (see next section).
LOW OUTPUT VOLTAGE AND C_F
The feed-forward capacitor C_F will provide a positive phase
shift (lead) which can be used to cancel some of the excess
phase lag from any of the various poles present in the loop.
However, it is important to note that the effectiveness of C_F
decreases with output voltage.
This is due to the fact that the frequencies of the zero f_zf and
pole f_pf get closer together as the output voltage is reduced
(see equations in section FEED-FORWARD COMPENSA-
TION).
C_F is more effective when the pole-zero pair are farther
apart, because there is less self cancellation. The net benefit
in phase shift provided by C_F is the difference between the
lead (positive phase shift) from f_zf and the lag (negative
phase shift) from f_pf which is present at the crossover fre-
quency f_c. As the pole and zero frequency approach each
other, that difference diminishes to nothing.
The amount of phase lead at f_C provided by C_F depends
both on the f_zf/f_pf ratio and the location of f_z with respect to f_c.
To illustrate this more clearly, a graph is provided which
shows how much phase lead can be obtained for V_OUT =
12V, 5V, and 3.3V (see graph PHASE LEAD PROVIDED BY
C_F).
Phase Lead Provided by C_F
DS100034-32
EXCESSIVE GATE CAPACITANCE: Higher values of gate
capacitance shift the pole f_pg to lower frequencies, which can
cause stability problems (see previous section GATE CA-
PACITANCE POLE FREQUENCY). As shown in the graph
f_pg vs. C_EFF, the pole f_pg will likely fall somewhere between
40 kHz and 500 kHz. How much phase shift this adds de-
pends on the crossover frequency f_c.
The effect of gate capacitance becomes most important at
high values of ESR for the output capacitor (see graph HIGH
ESR UNSTABLE WITHOUT FEED-FORWARD). Higher val-
ues of ESR increase f_c, which brings f_pg more into the posi-
tive gain portion of the curve. As f_pg moves to a lower fre-
quency (corresponding to higher values of gate
capacitance), this effect becomes even worse.
This points out why FET’s should be selected with the lowest
possible gate capacitance: it makes the design more tolerant
of higher ESR values on the output capacitor.
DS100034-33
The most important information on the graph is the fre-
quency range of f_zf which will provide the maximum benefit
(most positive phase shift):
For V_OUT = 12V: 0.1 f_c < f_z < 1.0 f_c
For V_OUT = 5V: 0.2 f_c < f_z < 1.2 f_c
For V_OUT = 3.3V: 0.2 f_c < f_z < 1.3 f_c
It’s also important to note how the maximum available phase
shift that C_F can provide drops off with V_OUT. At 12V, more
than 50˚ can be obtained, but at 3.3V less than 30˚ is pos-
sible. The lesson from this is that higher voltage designs are
more tolerant of phase shifts from both f_pg (the gate capaci-
tance pole) and incorrect placement of f_z (which means the
output capacitor ESR is not at its nominal value). At lower
values of V_OUT, these parameters must be more precisely
selected since C_F can not provide as much correction.
GENERAL DESIGN PROCEDURE
Assuming that V_IN, V_OUT, and R_L are defined:
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