LP2975 Datasheet, PDF (15/19 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

Application Hints (Continued)
that when the total phase shift at 0 dB reaches (or gets close
to) −180˚, oscillations will result. Therefore, it can be seen
that at least two poles in the gain curve are required to
cause instability.
ZERO: A zero has an effect that is exactly opposite to a pole.
A zero will add a maximum +90˚ of phase lead (defined as
positive phase shift). Also, a zero causes the slope of the
gain curve to increase by an additional +20 dB/decade (see
graph EFFECTS OF A SINGLE ZERO).
Effects of a Single Pole
STABILITY ANALYSIS OF TYPICAL APPLICATIONS
The first application to be analyzed is a fixed-output voltage
regulator with no feed-forward capacitor (see graph STABLE
PLOT WITHOUT FEED-FORWARD).
Stable Plot without Feed-Forward
DS100034-25
TOTAL PHASE SHIFT: The actual test of whether or not a
regulator is stable is the amount of phase shift that is present
when the gain curve crosses the 0 dB axis (the frequency
where this occurs was previously defined as f_c).
The phase shift at f_c can be estimated by looking at all of the
poles and zeroes on the Bode plot and adding up the contri-
butions of phase lag and lead from each one. As shown in
the graphs, most of the phase lag (or lead) contributed by a
pole (or zero) occurs within one decade of the frequency of
the pole (or zero).
In general, a phase margin (defined as the difference be-
tween the total phase shift and −180˚) of at least 20˚ to 30˚
is required for a stable loop.
Effects of a Single Zero
DS100034-27
In this example, the value of C_OUT is selected so that the
pole formed by C_OUT and R_L (previously defined as f_p) is set
at 200 Hz. The ESR of C_OUT is selected so that zero formed
by the ESR and C_OUT (defined as f_z) is set at 5 kHz (these
selections follow the general guidelines stated previously in
this document). Note that the gate capacitance is assumed
to be moderate, with the pole formed by the C_GATE (defined
as f_pg) occurring at 100 kHz.
To estimate the total phase margin, the individual phase shift
contributions of each pole and zero will be calculated assum-
ing f_p = 200 Hz, f_z = 5 kHz, f_c = 10 kHz and f_pg = 100 kHz:
Controller pole shift = −90˚
f_p shift = −arctan (10k/200) = −89˚
f_z shift = arctan (10k/5k) = +63˚
f_pg shift = −arctan (10k/100k) = −6˚
Summing the four numbers, the estimate for the total phase
shift is −122˚, which corresponds to a phase margin of 58˚.
This application is stable, but could be improved by using a
feed-forward capacitor (see next section).
EFFECT OF FEED-FORWARD: The example previously
used will be continued with the addition of a feed-forward ca-
pacitor C_F (see graph IMPROVED PHASE MARGIN WITH
FEED-FORWARD). The zero formed by C_F (previously de-
fined as f_zf) is set at 10 kHz and the pole formed by C_F (pre-
viously defined as f_pf) is set at 40 kHz (the 4X ratio of f_pf/f_zf
corresponds to V_OUT = 5V).
DS100034-26
15
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