LP2975 Datasheet, PDF (10/19 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

Reference Designs (Continued)
DS100034-41
Transient Response for 0–6A Load Step
Application Hints
SELECTING THE FET
The best choice of FET for a specific application will depend
on a number of factors:
VOLTAGE RATING: The FET must have a Drain-to-Source
breakdown voltage (sometimes called BV_DSS) which is
greater than the input voltage.
DRAIN CURRENT: On-state Drain current must be specified
to be greater than the worst-case (short circuit) load current
for the application.
TURN-ON THRESHOLD: The Gate-to-Source voltage
where the FET turns on (called the Gate Threshold Voltage)
is very important. Many FET’s are intended for use with
G-to-S voltages in the 5V to 10V range. These should only
be used in applications where the input voltage is high
enough to provide >5V of drive to the Gate.
Newer FET’s are becoming available with lower turn-on
thresholds (Logic-Level FET’s) which turn on fully with a gate
voltage of only 3V to 4V. Low threshold FET’s should be
used in applications where the input voltage is ≤ 5V.
ON RESISTANCE: FET on resistance (often called R_DSON)
is a critical parameter since it directly determines the mini-
mum input-to-output voltage required for operation at a given
load current (also called dropout voltage).
R_DSON is highly dependent on the amount of Gate-to-
Source voltage applied. For example, the R_DSON of a FET
with V_G-S = 5V will typically decrease by about 25% as the
V_G-S is increased to 10V. R_DSON is also temperature depen-
dent, increasing at higher temperatures.
The dropout voltage of any LDO design is directly related to
R_DSON, as given by:
V_DROPOUT = I_LOAD x (R_DSON + R_SC)
Where R_SC is the short-circuit current limit set resistor (see
Application Circuit).
GATE CAPACITANCE: Selecting a FET with the lowest pos-
sible Gate capacitance improves LDO performance in two
ways:
1) The Gate pin of the LP2975 (which drives the Gate of the
FET) has a limited amount of current to source or sink. This
means faster changes in Gate voltage (which corresponds to
faster transient response) will occur with a smaller amount of
Gate capacitance.
2) The Gate capacitance forms a pole in the loop gain which
can reduce phase margin. When possible, this pole should
be kept at a higher frequency than the cross-over frequency
of the regulator loop (see later section CROSS-OVER FRE-
QUENCY AND PHASE MARGIN).
A high value of Gate capacitance may require that a feedfor-
ward capacitor be used to cancel some of the excess phase
shift (see later section FEED-FORWARD CAPACITOR) to
prevent loop instability.
POWER DISSIPATION: The maximum power dissipated in
the FET in any application can be calculated from:
P_MAX = (V_IN − V_OUT) x I_MAX
Where the term I_MAX is the maximum output current. It
should be noted that if the regulator is to be designed to with-
stand short-circuit, a current sense resistor must be used to
limit I_MAX to a safe value (refer to section SHORT-CIRCUIT
CURRENT LIMITING).
The power dissipated in the FET determines the best choice
for package type. A TO-220 package device is best suited for
applications where power dissipation is less than 15W.
Power levels above 15W would almost certainly require a
TO-3 type device.
In low power applications, surface-mount package devices
are size-efficient and cost-effective, but care must be taken
to not exceed their power dissipation limits.
POWER DISSIPATION AND HEATSINKING
Since the LP2975 controller is suitable for use with almost
any external P-FET, it follows that designs can be built which
have very high power dissipation in the pass FET. Since the
controller can not protect the FET from overtemperature
damage, thermal design must be carefully done to assure a
reliable design.
THERMAL DESIGN METHOD: The temperature of the FET
and the power dissipated is defined by the equation:
Where:
T_J = (θ_J-A x P_D) + T_A
T_J is the junction temperature of the FET.
T_A is the ambient temperature.
P_D is the power dissipated by the FET.
θ_J-A is the junction-to-ambient thermal resistance.
To ensure a reliable design, the following guidelines are rec-
ommended:
1) Design for a maximum (worst-case) FET junction tem-
perature which does not exceed 150˚C.
2) Heatsinking should be designed for worst-case (maxi-
mum) values of T_A and P_D.
3) In designs which must survive a short circuit on the output,
the maximum power dissipation must be calculated assum-
ing that the output is shorted to ground:
P_D(MAX) = V_IN x I_SC
Where I_SC is the short-circuit output current.
4) If the design is not intended to be short-circuit proof, the
maximum power dissipation for intended operation will be:
P_D(MAX) = (V_IN − V_OUT) x I_MAX
Where I_MAX is the maximum output current.
LOW POWER (<2W) APPLICATIONS: In most cases,
some type of small surface-mount device will be used for the
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