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LP2975 Datasheet, PDF (13/19 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller
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Application Hints (Continued)
REQ = (R2 x 24k) / (R2 + 24k)
It follows that the output voltage will be:
VOUT = 1.24 [ (R1 / REQ) + 1]
Some important considerations for an adjustable design:
The tolerance of the internal 24 kΩ resistor is about ±20%.
Also, its temperature coefficient is almost certainly different
than the TC of the external resistor that is used for R2.
For these reasons, it is recommended that R2 be set at a
value that is not greater than 1.2k. In this way, the value of
R2 will dominate REQ, and the tolerance and TC of the inter-
nal 24k resistor will have a negligible effect on output voltage
accuracy.
To determine the value for R1:
R1 = REQ [ (VOUT / 1.24) − 1]
External Capacitors (Adjustable Application)
All information in the previous section EXTERNAL CAPACI-
TORS applies to the adjustable application with the excep-
tion of how to select the value of the feed-forward capacitor.
The feed-forward capacitor CC in the adjustable application
(see Typical Application Circuit) performs exactly the same
function as described in the previous section FEEDFOR-
WARD CAPACITOR. However, because R1 is user-
selected, a different formula must be used to determine the
value of CC:
CC = 1 / (2 π x R1 x fzf)
As stated previously, the optimal frequency at which to place
the zero fzf is usually between 5 kHz and 50 kHz.
OPTIMIZING DESIGN STABILITY
Because the LP2975 can be used with a variety of different
applications, there is no single set of components that are
best suited to every design. This section provides informa-
tion which will enable the designer to select components that
optimize stability (phase margin) for a specific application.
Gate Capacitance
An important consideration of a design is to identify the fre-
quency of the pole which results from the capacitance of the
Gate of the FET (this pole will be referred to as fpg). As fpg
gets closer to the loop crossover frequency, the phase mar-
gin is reduced. Information will now be provided to allow the
total Gate capacitance to be calculated so that fpg can be ap-
proximated.
The first step in calculating fp is to determine how much ef-
fective Gate capacitance (CEFF) is present. The formula for
calculating CEFF is:
CEFF = CGS + CGD [1 + Gm (RL / / ESR) ]
Where:
CGS is the Gate-to-Source capacitance, which is found
from the values (refer to FET data sheet for values of CISS
and CRSS):
CGS = CISS − CRSS
GGD is the Gate-to-Drain capacitance, which is equal to:
CGD = CRSS
Gm is the transconductance of the FET. The FET data
sheet specifies forward transconductance (Gfs) at some
value of drain current (defined as ID). To find Gm at the de-
sired value of load current (defined as IL), use the formula:
Gm = Gfs x (IL / ID)1/2
Where:
RL is the load resistance.
ESR is the equivalent series resistance of the output ca-
pacitor.
The term RL / / ESR is defined as:
(RL x ESR) / (RL + ESR)
It can be seen from these equations that CEFF varies with RL.
To get the worst-case (maximum) value for CEFF, use the
maximum value of load current, which also means the mini-
mum value of load resistance RL. It should be noted that in
most cases, the ESR is the dominant term which determines
the value of RL / / ESR.
Gate Pin Output Impedance
DS100034-20
Gate Capacitance Pole Frequency (fpg)
The pole frequency resulting from the Gate capacitance
CEFF is defined as fpg and can be approximated from:
fpg ≅ 0.16 / (RO x CEFF)
Where:
RO is the output impedance of the LP2975 Gate pin which
drives the Gate of the FET. It is important to note that RO is
a function of input supply voltage (see graph GATE PIN
OUTPUT IMPEDANCE). As shown, the minimum value of
RO is about 550Ω @ VIN = 24V, increasing to about 1.55 kΩ
@ VIN = 3V.
Using the equation for fpg, a family of curves are provided
showing how fpg varies with CEFF for several values of RO
(see graph fpg vs. CEFF):
fpg vs. CEFF
DS100034-21
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