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LP2975 Datasheet, PDF (16/19 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller
Application Hints (Continued)
Improved Phase Margin with Feed-Forward
High ESR Unstable without Feed-Forward
DS100034-28
To estimate the total phase margin, the individual phase shift
contributions of each pole and zero will be calculated assum-
ing fp = 200 Hz, fz = 5 kHz, fzf = 10 kHz, fpf = 40 kHz,
fc = 50 kHz, and fpg= 100 kHz:
Controller pole shift = −90˚
fp shift = −arctan (50k/200) = −90˚
fz shift = arctan (50k/5k) = +84˚
fzf shift = arctan (50k/100k) = +79˚
fpf shift = −arctan (50k/40k) = −51˚
fpg shift = −arctan (50k/100k) = −27˚
Summing the six numbers, the estimate for the total phase
shift is −95˚, which corresponds to a phase margin of 85˚
(a 27˚ improvement over the same application without the
feed-forward capacitor).
For this reason, a feed-forward capacitor is recommended in
all applications. Although not always required, the added
phase margin typically gives faster settling times and pro-
vides some design guard band against COUT and ESR varia-
tions with temperature.
CAUSES AND CURES OF OSCILLATIONS
The most common cause of oscillations in an LDO applica-
tion is the output capacitor ESR. If the ESR is too high or too
low, the zero (fz) does not provide enough phase lead.
HIGH ESR: To illustrate the effect of an output capacitor with
high ESR, the previous example will be repeated except that
the ESR will be increased by a factor of 20X. This will cause
the frequency of the zero fz to decrease by 20X, which
moves it from 5 kHz down to 250 Hz (see graph HIGH ESR
UNSTABLE WITHOUT FEED-FORWARD).
DS100034-29
As shown, moving the location of fz lower in frequency ex-
tends the bandwidth, pushing the crossover frequency fc out
to about 200 kHz. In viewing the plot, it can be seen that fp
and fz essentially cancel out, leaving only the controller pole
and fpg. However, since fpg now occurs well before fc, it will
cause enough phase shift to leave very little phase margin.
This application would either oscillate continuously or be
marginally stable (meaning it would exhibit severe ringing on
transient steps).
This can be improved by adding a feed-forward capacitor CF,
which adds a zero (fzf) and a pole (fpf) to the gain plot (see
graph HIGH ESR CORRECTED WITH FEED-FORWARD).
In this case, CF is selected to place fzf at about the same fre-
quency as fpg (essentially cancelling out the phase shift due
to fpg). Assuming the added pole fpf is near or beyond the fc
frequency, it will add < 45˚ of phase lag, leaving a phase
margin of > 45˚ (adequate for good stability).
High ESR Corrected with Feed-Forward
DS100034-31
LOW ESR: To illustrate how an output capacitor with low
ESR can cause an LDO regulator to oscillate, the same ex-
ample will be shown except that the ESR will be reduced suf-
ficiently to increase the original fz from 5 kHz to 50 kHz.
The plot now shows (see graph LOW ESR UNSTABLE
WITHOUT FEED-FORWARD) that the crossover frequency
fc has moved down to about 8 kHz. Since fz is 6X fc, it means
that the zero fz can only provide about 9˚ of phase lead at fc,
which is not sufficient for stability.
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