LP2975 Datasheet, PDF (14/19 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

Application Hints (Continued)
As can be seen in the graph, values of C_EFF in the
500 pF–2500 pF range produce values for f_pg between
40 kHz and 700 kHz. To determine what effect f_pg will have
on stability, the bandwidth of the regulator loop must be cal-
culated (see next section CROSSOVER FREQUENCY AND
PHASE MARGIN).
Crossover Frequency and Phase Margin
The term f_c will be used to define the crossover frequency of
the regulator loop (which is the frequency where the gain
curve crosses the 0 dB axis). The importance of this fre-
quency is that it is the point where the loop gain goes below
unity, which marks the usable bandwidth of the regulator
loop.
It is the phase margin (or lack of it) at f_c that determines
whether the regulator is stable. Phase margin is defined as
the total phase shift subtracted from 180˚. In general, a
stable loop requires at least 20˚-30˚ of phase margin at f_c.
f_c can be approximated by the following equation (all terms
have been previously defined):
DS100034-23
This equation assumes that no C_F is used and f_pg/f_c > 1.
If the frequency of the Gate capacitance pole f_pg has been
calculated (previous section), the amount of added phase
shift may now be determined. As shown in the graph below
(see graph PHASE SHIFT DUE TO f_pg), the amount of
added phase shift increases as f_pg approaches f_c.
The amount of phase shift due to f_pg that can occur before
oscillation takes place depends on how much added phase
shift is present as a result of the C_OUT pole (see previous
section OUTPUT CAPACITOR).
Phase Shift Due to f_pg
DS100034-22
Because of this, there is no exact number for f_pg/f_c that can
be given as a fixed limit for stable operation. However, as a
general guideline, it is recommended that f_pg ≥ 3 f_c.
If this is not found to be true after inital calculations, the ratio
of f_pg/f_c can be increased by either reducing C_EFF (selecting
a different FET) or using a larger value of C_OUT.
Along with these two methods, another technique for improv-
ing loop stability is the use of a feed-forward capacitor (see
next section FEED-FORWARD COMPENSATION). This can
improve phase margin by cancelling some of the excess
phase shift.
Feed-Forward Compensation
Phase shift in the loop gain of the regulator results from f_p
(the pole from the output capacitor and load resistance), f_pg
(the pole from the FET gate capacitance), as well as the IC’s
internal controller pole (see typical curve). If the total phase
shift becomes excessive, instability can result.
The total phase shift can be reduced using feed-forward
compensation, which places a zero in the loop to reduce the
effects of the poles.
The feed-forward capacitor C_F can accomplish this, provided
it is selected to set the zero at the correct frequency. It is im-
portant to point out that the feed-forward capacitor produces
both a zero and a pole. The frequency where the zero occurs
will be defined as f_zf, and the frequency of the pole will be
defined as f_pf. The equations to calculate the frequencies
are:
f_zf = 6.6 x 10^-6/ [C_F x (V_OUT/1.24 − 1) ]
f_pf = 6.6 x 10^-6/ [C_F x (1 − 1.24/V_OUT)]
In general, the feed-forward capacitor gives the greatest im-
provement in phase margin (provides the maximum reduc-
tion in phase shift) when the zero occurs at a frequency
where the loop gain is >1 (before the crossover frequency).
The pole must occur at a higher frequency (the higher the
better) where most of the phase shift added by the new pole
occurs beyond the crossover frequency. For this reason, the
pole-zero pair created by C_F become more effective at im-
proving loop stability as they get farther apart in frequency.
In reviewing the equations for f_zf and f_pf, it can be seen that
they get closer together in frequency as V_OUT decreases.
For this reason, the use of C_F gives greatest benefit at higher
output voltages, declining as V_OUT approaches 1.24V
(where C_F has no effect at all).
In selecting a value of feed-forward capacitor, the crossover
frequency f_c must first be calculated. In general, the fre-
quency of the zero (f_zf) set by this capacitor should be in the
range:
0.2 f_c ≤ f_zf ≤ 1.0 f_c
The equation to determine the value of the feed-forward ca-
pacitor in fixed-voltage applications is:
C_F = 6.6 x 10^-6/ [f_zf x (V_OUT/1.24 − 1) ]
In adjustable applications (using an external resistive di-
vider) the capacitor is found using:
C_C = 1/(2 π x R1 x f_zf)
SUMMARY OF STABILITY INFORMATION
This section will present an explanation of theory and termi-
nology used to analyze loop stability, along with specific in-
formation related to stabilizing LP2975 applications.
BODE PLOTS AND PHASE SHIFT
Loop gain information is most often presented in the form of
a Bode Plot, which plots Gain (in dB) versus Frequency (in
Hertz).
A Bode Plot also conveys phase shift information, which can
be derived from the locations of the poles and zeroes.
POLE: A pole causes the slope of the gain curve to de-
crease by an additional −20 dB/decade, and it also causes
phase lag (defined as negative phase shift) to occur.
A single pole will cause a maximum −90˚ of phase lag (see
graph EFFECTS OF A SINGLE POLE). It should be noted
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