COP410L Datasheet, PDF (15/20 Pages) National Semiconductor (TI) – Single-Chip N-Channel Microcontrollers

Instruction Set (Continued)
TABLE III COP410L 411L Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
TRANSFER OF CONTROL INSTRUCTIONS
JID
FF
x 1111 1111 ROM (PC₈ A M)
None
PC_{7 0}
JMP
a
6–
x 0110 000 a₈ a PC
––
a_{7 0}
None
JP
a
––
1 a6 0
x a
PC_{6 0}
(pages 2 3 only)
or
––
11 a5 0
x a
PC_{5 0}
(all other pages)
None
Description
Jump Indirect (Note 2)
Jump
Jump within Page
(Note 3)
JSRP
JSR
a
––
10 a5 0
PC a 1 x SA x SB None
x 010
PC_{8 6}
x a
PC_{5 0}
a
6–
x x 0110 100 a₈ PC a 1 SA SB None
––
a_{7 0}
a x PC
Jump to Subroutine Page
(Note 4)
Jump to Subroutine
RET
48
0100 1000 SB x SA x PC
None
Return from Subroutine
RETSK
49
0100 1001 SB x SA x PC
MEMORY REFERENCE INSTRUCTIONS
CAMQ
33
0011 0011
3C
0011 1100
LD
r
–5
00 r 0101
x A
Q_{7 4}
x RAM(B)
Q_{3 0}
RAM(B) x A
x Br Z r
Br
Always Skip on Return Return from Subroutine
then Skip
None
None
Copy A RAM to Q
Load RAM into A
Exclusive-OR Br with r
LQID
BF
x 1011 1111 ROM(PC₈ A M) Q None
SA x SB
Load Q Indirect (Note 2)
RMB
SMB
STII
0
4C
x 0100 1100 0 RAM(B)₀
1
45
x 0100 0101 0 RAM(B)₁
2
42
x 0100 0010 0 RAM(B)₂
3
43
x 0100 0011 0 RAM(B)₃
0
4D
x 0100 1101 1 RAM(B)₀
1
47
x 0100 0111 1 RAM(B)₁
2
46
x 0100 0110 1 RAM(B)₂
3
4B
x 0100 1011 1 RAM(B)₃
y
7–
0111 y
y x RAM(B)
Bd a 1 x Bd
None
None
None
Reset RAM Bit
Set RAM Bit
Store Memory Immediate
and Increment Bd
X
r
–6
00 r 0110 RAM(B)
A
None
x Br Z r
Br
Exchange RAM with A
Exclusive-OR Br with r
XAD
3 15
23
0010 0011 RAM(3 15)
A
BF
1011 1111
None
Exchange A with RAM
(3 15)
XDS
r
–7
00 r 0111 RAM(B)
A
Bd – 1 x Bd
x Br Z r
Br
Bd decrements past 0 Exchange RAM with A
and Decrement Bd
Exclusive-OR Br with r
XIS
r
–4
00 r 0100 RAM(B)
A
Bd increments past 15 Exchange RAM with A
Bd a 1 x Bd
and Increment Bd
x Br Z r
Br
Exclusive-OR Br with r
15