COP410L Datasheet, PDF (11/20 Pages) National Semiconductor (TI) – Single-Chip N-Channel Microcontrollers

L-Bus Considerations
False states may be generated on L₀ – L₇ during the execu-
tion of the CAMQ instruction The L-ports should not be
used as clocks for edge sensitive devices such as flip-flops
counters shift registers etc the following short program
that illustrates this situation
START
CLRA
ENABLE THE Q
LEI 4
REGISTER TO L LINES
LBI TEST
STII 3
AISC 12
LOOP
LBI TEST LOAD Q WITH X’C3
CAMQ
JP LOOP
Typical Performance Characteristics
In this program the internal Q register is enabled onto the L
lines and a steady bit pattern of logic highs is output on L₀
L₁ L₆ L₇ and logic lows on L₂ – L₅ via the two-byte CAMQ
instruction Timing constraints on the device are such that
the Q register may be temporarily loaded with the second
byte of the CAMQ opcode (X 3C) prior to receiving the valid
data pattern If this occurs the opcode will ripple onto the L
lines and cause negative-going glitches on L₀ L₁ L₆ L₇
and positive glitches on L₂ – L₅ Glitch durations are under
2 ms although the exact value may vary due to data pat-
terns processing parameters and L line loading These
false states are peculiar only to the CAMQ instruction and
the L lines
Input Current RESET SI
Input Current for L0 through
L7 when Output Programmed
Off by Software
Source Current for Standard
Output Configuration
Source Current for SO
and SK in Push-Pull
Configuration
Source Current for L0 through
L7 in TRI-STATE Configuration
(High Current Option)
Source Current for L0 through
L7 in TRI-STATE Configuration
(Low Current Option)
FIGURE 8a COP410L COP411L I O DC Current Characteristics
TL DD 6919 – 18
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