SM5849F Datasheet, PDF (4/26 Pages) Nippon Precision Circuits Inc – Asynchronous Sample Rate Converter

BLOCK DIAGRAM
SM5849AF
MCOM
MDT/FSI1
MCK/FSI2
MLEN/DEEM
ICLK
ICKSL
IWL1 IWL2 IFM1 IFM2
BCKI
DI
Deemphasis and
attenuator setup
Input-stage
divider
Input data
interface
Arithmetic
operations
Deemphasis
operation
LRCI
RSTN
Input timing
controller
DITHN
TST2N
Filter characteristic
select
Output operation
timing controller
OWL1
OWL2
IISN
Output format
controller
SLAVE
Output-stage
clock select
Attenuator
Interpolation
filter operation
Dither
operation
Output
operation
Output data
interface
LRCI BCKI DI
OCLK
OCKSL
THRUN
DMUTE
Output-stage
divider
Mute
generator
LRCO
BCKO
Through mode
switching
Direct mute
DOUT
STATE
NIPPON PRECISION CIRCUITS—4