SM5849F Datasheet, PDF (21/26 Pages) Nippon Precision Circuits Inc – Asynchronous Sample Rate Converter

SM5849AF
Filter Characteristic Selection
Conversion rates from 0.45 to 2.2 times are sup-
ported using the following 6 filter types.
The ratio between the output sample rate and input
sample rate is measured automatically and the most
suitable filter type for this ratio is selected automati-
cally.
Table 13. fs ratio and filter selection
Filter
mode
1
2
3
4
5
6
fs ratio (fso/fsi)
1.0 to 2.2
0.91875
0.72562
0.66667
0.50000
0.459375
Selects range
≥ 0.969697
0.864865 to
0.969697
0.711111 to
0.864865
0.627451 to
0.711111
0.492308 to
0.627451
≤ 0.492308
Conversion
frequency
(example)
Up converter
48.0 to 44.1kHz
44.1 to 32.0kHz
48 to 32kHz
48 to 24kHz,
96 to 48kHz
48 to 22.05kHz,
96 to 44.1kHz
When the selected fs conversion ratio and the actual
sample rate conversion ratio do not coincide, the fol-
lowing phenomenon occur.
Table 14. Mismatch condition and response
Condition¹
Response
Actual sample rate conversion
ratio is low er than the selected
filter conversion ratio
The audio band high-pass
develops aliasing noise.
Actual sample rate conversion
ratio is higher than the selected
filter conversion ratio
The audio band high-pass is cut
off.
1. An output noise may be generated if the fs conversion ratio changes at
a rate greater 0.119%/sec.
System Reset (RSTN)
At power-ON, all device functions must be reset. The
device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic opera-
tion, output timing counter and internal flag register
operation are synchronized on the next LRCI rising
edge. Note that all flags are set to their defaults (all
LOW).
Through Mode (THRUN)
A power-ON reset signal can be applied from an
external microcontroller. For systems where ICLK
and LRCI are stable at power ON, initialization can
be performed by connecting a 0.001µF capacitor
between RSTN and VSS. Otherwise, a capacitor
value should be chosen such that RSTN does not go
HIGH until after LRCI and ICLK have stabilized.
Table 15. Through mode function description
THRUN
LOW
HIGH
Mode
Through mode
Normal mode
Description
Direct connections are made: LRCI
to LRCO, BCKI to BCKO , and DI to
D O U T. DMUTE is valid.
Sample rate converter operation
Synchronizing Internal Arithmetic Timing
The clock on LRCI should pass through 1 cycle for
every 384 (ICKSL = HIGH) or 256 (ICKSL = LOW)
ICLK clock cycles to maintain correct internal arith-
metic sequence. If the number of ICLK cycles is dif-
ferent, increases or decreases, or any jitter is present,
device operation could be affected.
There is a fixed-value tolerance within which the
internal sequence and LRCI clock timing are not
adversely affected.
Table 16. ICLK and clock tolerance
ICKSL
HIGH (384fs mode)
LOW (256fs mode)
Allowable clock variation
+8 to −6 cycles
+4 to −3 cycles
Whenever the allowable tolerance is exceeded, the
internal sequence start-up may be delayed or fail.
When this occurs, there is a possibility that a click
noise will be generated.
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