SM5849F Datasheet, PDF (20/26 Pages) Nippon Precision Circuits Inc – Asynchronous Sample Rate Converter

SM5849AF
Output Data Interface and Output Clock Selection (LRCO, BCKO, DOUT, SLAVE)
Table 12. Output mode description
THRUN
SLAVE
Mode
Function
Description
LRCO, BCKO state
HIGH
LOW
HIGH
Master mode
Slave mode
Output word clock (LRCO) and output bit clock
(BCKO) are divided from OCLK.
Output word clock (LRCO) and output bit clock
( B C KO) are supplied externally.
Outputs
Inputs¹
Output word clock (LRCO), output bit clock (BCKO)
LOW
×
Through mode
and output data (DOUT) are the same as LRCI,
Outputs
BCKI and DI, respectively. DMUTE is valid.
1. The number of BCKO input clock cycles should not exceed 64 per word. Correct operation is not guaranteed beyond these limits.
Output Format Control (OWL1, OWL2, IISN)
The output is in MSB-first, 2s-complement, L/R
alternating, bit serial format with a continuous bit
clock.
Inputs
Output format
Mode
IISN
OWL2
OWL1
W ord IIS
length selection
Data
position
1
LOW LOW 16 bits
2
3
LOW
HIGH
HIGH
HIGH 20 bits _Normal
LOW 24 bits ^{(non IIS)}
Right
justified
4
HIGH HIGH 24 bits
5
LOW LOW 16 bits
6 LOW LOW HIGH 20 bits IIS
Left
justified
7
HIGH × 24 bits
Output Timing Calculation
The output timing is controlled to maintain the
desired ratio between the output data cycle and the
input data cycle.
Output round-off processing
The internal processor data length and output data
length are different, making output data round-off
processing necessary. The SM5849AF supports
selectable normal round-off processing and trigono-
metric function dither round-off processing^*.
*_{TPDF: Triangular Probability Density Function}
DITHN
HIGH
LOW
Output round-off processing
Normal round-off
Dither round-off
NIPPON PRECISION CIRCUITS—20